Quasi-cyclic low-density parity-check （QC-LDPC） codes can be constructed conveniently by cyclic lifting of protographs. For the purpose of eliminating short cycles in the Tanner graph to guarantee performance, first...Quasi-cyclic low-density parity-check （QC-LDPC） codes can be constructed conveniently by cyclic lifting of protographs. For the purpose of eliminating short cycles in the Tanner graph to guarantee performance, first an algorithm to enumerate the harmful short cycles in the protograph is designed, and then a greedy algorithm is proposed to assign proper permutation shifts to the circulant permutation submatrices in the parity check matrix after lifting. Compared with the existing deterministic edge swapping （DES） algorithms, the proposed greedy algorithm adds more constraints in the assignment of permutation shifts to improve performance. Simulation results verify that it outperforms DES in reducing short cycles. In addition, it is proved that the parity check matrices of the cyclic lifted QC-LDPC codes can be transformed into block lower triangular ones when the lifting factor is a power of 2. Utilizing this property, the QC- LDPC codes can be encoded by preprocessing the base matrices, which reduces the encoding complexity to a large extent.展开更多
Objective To evaluate left atrial function in essential hypertension patients with different patterns of left ventricular geometric models by real-time three-dimensional echocardiography （RT-3DE） and left atrial tra...Objective To evaluate left atrial function in essential hypertension patients with different patterns of left ventricular geometric models by real-time three-dimensional echocardiography （RT-3DE） and left atrial tracking （EAT）.展开更多
In order to increase the efficiency and reliability of the dynamic analysis for flexible planar linkage containing the coupling of multi-energy domains, a method based on bond graph is introduced. From the viewpoint o...In order to increase the efficiency and reliability of the dynamic analysis for flexible planar linkage containing the coupling of multi-energy domains, a method based on bond graph is introduced. From the viewpoint of power conservation, the peculiar property of bond graph multiport element MTF is discussed. The procedure of modeling planar flexible muhibody mechanical systems by bond graphs and its dynamic principle are deseribed. To overcome the algebraic difficulty brought by differential causality anti nonlinear junction structure, the constraint forces at joints can be considered as unknown effort sources and added to the corresponding O-junctions of system bond graph model. As a result, the automatic modeling on a computer is realized. The validity of the procedure is illustrated by a practical example.展开更多
Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Cus...Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network con- taining hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.展开更多
基金The National Key Technology R&D Program of China during the 12th Five-Year Plan Period(No.2012BAH15B00)
文摘Quasi-cyclic low-density parity-check （QC-LDPC） codes can be constructed conveniently by cyclic lifting of protographs. For the purpose of eliminating short cycles in the Tanner graph to guarantee performance, first an algorithm to enumerate the harmful short cycles in the protograph is designed, and then a greedy algorithm is proposed to assign proper permutation shifts to the circulant permutation submatrices in the parity check matrix after lifting. Compared with the existing deterministic edge swapping （DES） algorithms, the proposed greedy algorithm adds more constraints in the assignment of permutation shifts to improve performance. Simulation results verify that it outperforms DES in reducing short cycles. In addition, it is proved that the parity check matrices of the cyclic lifted QC-LDPC codes can be transformed into block lower triangular ones when the lifting factor is a power of 2. Utilizing this property, the QC- LDPC codes can be encoded by preprocessing the base matrices, which reduces the encoding complexity to a large extent.
基金Supported by the Natural Science Foundation of Liaoning ProvinceChina(2013023010)
文摘Objective To evaluate left atrial function in essential hypertension patients with different patterns of left ventricular geometric models by real-time three-dimensional echocardiography （RT-3DE） and left atrial tracking （EAT）.
文摘In order to increase the efficiency and reliability of the dynamic analysis for flexible planar linkage containing the coupling of multi-energy domains, a method based on bond graph is introduced. From the viewpoint of power conservation, the peculiar property of bond graph multiport element MTF is discussed. The procedure of modeling planar flexible muhibody mechanical systems by bond graphs and its dynamic principle are deseribed. To overcome the algebraic difficulty brought by differential causality anti nonlinear junction structure, the constraint forces at joints can be considered as unknown effort sources and added to the corresponding O-junctions of system bond graph model. As a result, the automatic modeling on a computer is realized. The validity of the procedure is illustrated by a practical example.
基金Project supported by the Hi-Tech Research and Development Pro-gram (863) of China (No. 2002AA1Z1140)the Fok Ying TongEducation Foundation (No. 94031), China
文摘Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network con- taining hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.
