提出了一种具有双槽栅(DTG)SOI LDMOS新结构及其制造方法。与单槽栅(STG)SOI LDMOS相比,DTG SOI LDMOS具有更高的击穿电压,更低的通态电阻,更高的跨导。通过Silvaco TCAD对该结构进行了工艺仿真和器件电学特性模拟,结果表明DTG SOI LDMO...提出了一种具有双槽栅(DTG)SOI LDMOS新结构及其制造方法。与单槽栅(STG)SOI LDMOS相比,DTG SOI LDMOS具有更高的击穿电压,更低的通态电阻,更高的跨导。通过Silvaco TCAD对该结构进行了工艺仿真和器件电学特性模拟,结果表明DTG SOI LDMOS器件不仅具有较好的电学性能,而且可以采用SOI CMOS工艺制造。展开更多
A buried-oxide trench-gate bipolar-mode JFET （BTB-JFET） with an oxide layer buried under the gate region to reduce the gate-drain capacitance Cgd is proposed. Simulations with a resistive load circuit for power loss...A buried-oxide trench-gate bipolar-mode JFET （BTB-JFET） with an oxide layer buried under the gate region to reduce the gate-drain capacitance Cgd is proposed. Simulations with a resistive load circuit for power loss comparison at high frequency application are performed with 20V-rated power switching devices,including a BTB-JFET,a trench MOSFET （T-MOSFET） generally applied in present industry, and a conventional trench-gate bipolar-mode JFET （TB-JFET） without buried oxide,for the first time. The simulation results indicate that the switching power loss of the normally-on BTB-JFET is improved by 37% and 14% at 1MHz compared to the T-MOSFET and the normally-on TB-JFET, respectively. In order to demonstrate the validity of the simulation, the normally-on TB-JFET and BTB-JFET have been fabricated successfully for the first time, where the buried oxide structure is realized by thermal oxidation. The experimental results show that the Cgd of the BTB-JFET is decreased by 45% from that of the TB-JFET at zero source-drain bias. Compared to the TB-JFET,the switching time and switching power loss of the BTB-JFET decrease approximately by 7. 4% and 11% at 1MHz,respectively. Therefore,the normally-on BTB-JFET could be pointing to a new direction for the R＆D of low volt- age and high frequency switching devices.展开更多
文摘提出了一种具有双槽栅(DTG)SOI LDMOS新结构及其制造方法。与单槽栅(STG)SOI LDMOS相比,DTG SOI LDMOS具有更高的击穿电压,更低的通态电阻,更高的跨导。通过Silvaco TCAD对该结构进行了工艺仿真和器件电学特性模拟,结果表明DTG SOI LDMOS器件不仅具有较好的电学性能,而且可以采用SOI CMOS工艺制造。
文摘A buried-oxide trench-gate bipolar-mode JFET （BTB-JFET） with an oxide layer buried under the gate region to reduce the gate-drain capacitance Cgd is proposed. Simulations with a resistive load circuit for power loss comparison at high frequency application are performed with 20V-rated power switching devices,including a BTB-JFET,a trench MOSFET （T-MOSFET） generally applied in present industry, and a conventional trench-gate bipolar-mode JFET （TB-JFET） without buried oxide,for the first time. The simulation results indicate that the switching power loss of the normally-on BTB-JFET is improved by 37% and 14% at 1MHz compared to the T-MOSFET and the normally-on TB-JFET, respectively. In order to demonstrate the validity of the simulation, the normally-on TB-JFET and BTB-JFET have been fabricated successfully for the first time, where the buried oxide structure is realized by thermal oxidation. The experimental results show that the Cgd of the BTB-JFET is decreased by 45% from that of the TB-JFET at zero source-drain bias. Compared to the TB-JFET,the switching time and switching power loss of the BTB-JFET decrease approximately by 7. 4% and 11% at 1MHz,respectively. Therefore,the normally-on BTB-JFET could be pointing to a new direction for the R＆D of low volt- age and high frequency switching devices.
