设计了一种适用于过高磁场抗扰度的电容式隔离型全差分Σ-Δ调制器。它采用单环2阶1位量化的前馈积分器结构,运用斩波技术降低低频噪声和直流失调。与传统的全差分结构相比,该调制器的每级积分器均采用4个采样电容,在一个时钟周期内能...设计了一种适用于过高磁场抗扰度的电容式隔离型全差分Σ-Δ调制器。它采用单环2阶1位量化的前馈积分器结构,运用斩波技术降低低频噪声和直流失调。与传统的全差分结构相比,该调制器的每级积分器均采用4个采样电容,在一个时钟周期内能实现两次采样与积分,所需的外部时钟频率仅为传统积分器的一半,降低了运放的压摆率及单位增益带宽的设计要求,实现了低功耗。基于CSMC 0.35μm CMOS工艺,在5 V电源电压、10 MHz采样频率和256过采样率的条件下进行电路仿真。后仿真结果表明,调制器的SNDR为100.7 d B,THD为-104.9 d B,ENOB可达16.78位,总功耗仅为0.4 m A。展开更多
The time-optimal control design of the double integrator is extended to the finite-time stabilization design that compensates both input saturation and input delay. With the aid of the Artstein's transformation, t...The time-optimal control design of the double integrator is extended to the finite-time stabilization design that compensates both input saturation and input delay. With the aid of the Artstein's transformation, the problem is reduced to assigning a saturated finite-time stabilizer.展开更多
文摘设计了一种适用于过高磁场抗扰度的电容式隔离型全差分Σ-Δ调制器。它采用单环2阶1位量化的前馈积分器结构,运用斩波技术降低低频噪声和直流失调。与传统的全差分结构相比,该调制器的每级积分器均采用4个采样电容,在一个时钟周期内能实现两次采样与积分,所需的外部时钟频率仅为传统积分器的一半,降低了运放的压摆率及单位增益带宽的设计要求,实现了低功耗。基于CSMC 0.35μm CMOS工艺,在5 V电源电压、10 MHz采样频率和256过采样率的条件下进行电路仿真。后仿真结果表明,调制器的SNDR为100.7 d B,THD为-104.9 d B,ENOB可达16.78位,总功耗仅为0.4 m A。
基金partially supported by the National Natural Science Foundation of China(61374024,61321003,61325309)the Natural Science Foundation of Hunan Province(14JJ2016)the Teacher Research Foundation of Central South University(2013JSJJ023)
文摘The time-optimal control design of the double integrator is extended to the finite-time stabilization design that compensates both input saturation and input delay. With the aid of the Artstein's transformation, the problem is reduced to assigning a saturated finite-time stabilizer.