针对永磁同步电机(permanent magnetic synchronous motor,PMSM)无位置传感器控制中转子初始位置难以精确估算的问题,提出了一种基于注入变频方波电压的双锁相环结构转子位置估算的方案。首先对电机施加振幅相同方向相反的低频方波电压...针对永磁同步电机(permanent magnetic synchronous motor,PMSM)无位置传感器控制中转子初始位置难以精确估算的问题,提出了一种基于注入变频方波电压的双锁相环结构转子位置估算的方案。首先对电机施加振幅相同方向相反的低频方波电压判别转子极性。然后提高方波电压频率至3 kHz,使用一种新型的双锁相环结构对转子位置估算值进行适应性误差补偿,以提高估算精度。最后保持高频信号注入进行电机空载、负载启动,全程无需中断和改变注入信号。实验表明,该方法对转子初始位置估算误差最大不超过3.73°,平均估算时间为0.18 s,估算过程中电机保持静止。当电机启动时,双锁相环结构比传统锁相环结构估算时间缩短18 ms,最大补偿角度为38.39°。估算过程未引入电机敏感参数,系统具有良好的稳定性和快速性。展开更多
An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods ...An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.展开更多
Dual-modulus prescalers （DMP） for RF receivers are studied. An improved D-latch is proposed to increase the speed and the driving capability of the DMP. A novel D-latch architecture integrated with ‘OR＇ logic is p...Dual-modulus prescalers （DMP） for RF receivers are studied. An improved D-latch is proposed to increase the speed and the driving capability of the DMP. A novel D-latch architecture integrated with ‘OR＇ logic is proposed to decrease the complexity of the circuit. A divided-by-16/17 DMP for application in a digital video broadcasting-terrestrial receiver is realized with a TSMC 0.18μm mixed-signal CMOS process. The programmable ＆ pulse swallow divider in this receiver is designed with a 0.18μm CMOS standard cell library and realized in the same process. The measured results show that the DMP has an output jitter of less than 0.03% and works well with the programmable ＆ pulse swallow divider.展开更多
文摘针对解耦双同步参考坐标系锁相环DDSRF-PLL(decoupled double synchronous reference frame phaselocked loop)在电网电压畸变时锁相存在较大偏差问题,提出一种频率自适应锁相技术。首先设计了一种用于滤除电网多次谐波和直流电压的新型基于二阶广义积分器的正交信号发生器NSOGI-QSG(novel second order gen?eralized integrator-quadrature signal generator),在此基础上提出一种将NSOGI-QSG与DDSRF-PLL结合的频率自适应锁相环,利用NSOGI-QSG形成频率自适应滤波器和直流控制器,有效实现频率自适应和畸变电压滤波,为解耦双同步参考坐标系锁相环提供稳定的正交信号,从而提高锁相环抑制电网电压畸变的能力。理论分析和仿真结果验证了该方法的正确性和有效性。
文摘An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.
文摘Dual-modulus prescalers （DMP） for RF receivers are studied. An improved D-latch is proposed to increase the speed and the driving capability of the DMP. A novel D-latch architecture integrated with ‘OR＇ logic is proposed to decrease the complexity of the circuit. A divided-by-16/17 DMP for application in a digital video broadcasting-terrestrial receiver is realized with a TSMC 0.18μm mixed-signal CMOS process. The programmable ＆ pulse swallow divider in this receiver is designed with a 0.18μm CMOS standard cell library and realized in the same process. The measured results show that the DMP has an output jitter of less than 0.03% and works well with the programmable ＆ pulse swallow divider.
