电子显微镜自动停机系统的设计

本系统设计采用CMOS集成电路CD4060为中心的分频与振荡器及延时控制系统,解决了扫描电子显微镜延时自动停机及加热后冷却问题.极大地减轻使用者的不便和延长电子显微镜真空系统的寿命.

A Novel Digital Transceiver for CT0 Standard

This paper introduces a novel digital transceiver for the cordless telephone zero （CT0） standard,which uses a digital modulation and demodulation technique to handle the signal instead of the traditional analog meth-od. In the transmitter,a fractional-N phase locked loop （PLL） is utilized to realize the continuous phase frequency shift key （CPFSK） modulation,and a 2 Ts raised cosine （2RC） shaping technique is used to reduce the occupied bandwidth. In the receiver,a novel digital method is proposed to demodulate the 2RC CPFSK signal. This chip is fabricated using an SMIC 0.35μm mixed signal CMOS process with a die size of 2mm × 2mm. With an external low noise amplifier （LNA）,the sensitivity of the chip is better than -103dBm.

Low Voltage CMOS Gilbert Mixers for Bluetooth Transceiver

Based on the analyses of the reported Gilbert mixers operating at low supply vol tage,a down-conversion mixer and an up-conversion mixer for 2.4GHz bluetooth transceiver are presented with the modified low voltage design techniques,respe ctively.Feedback and current mirror techniques suitable for low voltage operatio n are used to improve the linearity of the up-conversion mixer,and folded-casc ode output stage is adopted to optimize the noise and conversion gain of the dow n-conversion mixer operating at low voltage.Based on 0.35μm CMOS technology,s imulations are performed with 2V supply voltage.The results show that 20dBm thir d-order intercept point (IIP3),87mV output signal amplitude are achieved for up -conversion mixer with about 3mA current;while 20dB conversion gain (CG),6.5nV /Hz input-referred noise,4.4dBm IIP3 are obtained for down-conversion mixer with about 3.5mA current.

CMOS Mixers for 2.4GHz WLAN Transceivers

A down-conversion mixer and an up-conversion mixer for 2.4GHz WLAN transceivers are presented.The down-conversion mixer uses a class-AB input stage to get high linearity and to realize input impedance matching and single-ended to differential conversion.The mixers are implemented in 0.18μm CMOS process.The measured results are given to show their performance.

A CMOS Power Amplifier with 100% and 18% Modulation Depth for Mobile RFID Readers

Aiming at the specific protocol of RFID technology,a 915MHz CMOS transmitter front-end for OOK modulation is implemented in a 0.18μm CMOS process. The transmitter incorporates a class-E power amplifier （PA）, a modulator, and a control logic unit. The direct-conversion architecture minimizes the required on-and-off-chip components and provides a low-cost and efficient solution. A novel structure is proposed to provide the modulation depth of 100% and 18% ,respectively. The PA presents an output ldB power of 17.6dBm while maintaining a maximum PAE of 35.4%.

Integrated Low-Power CMOS VCO and Its Divide-by-2 Dividers

An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.

An 8.5GHz 1∶8 Frequency Divider in 0.35μm CMOS Technology

An 1∶8 frequency divider is designed and realized in a 0 35μm standard CMOS technology.The chip consists of three stages of 1∶2 divider cells,which are constructed with source couple logic (SCL) flip flops.By revising the traditional topology of SCL flip flop,a divider with better performances is got.The results of measurement show that the whole chip achieves the frequency division at more than 8 5GHz.Each 1∶2 divider consumes about 11mW from a 3 3V supply.The divider can be used in RF and optic fiber transceivers and other high speed systems.

A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications

A 2. 4GHz CMOS monolithic transceiver front-end for IEEE 802. llb wireless LAN applications is presented. The receiver and transmitter are both of superheterodyne structure for good system performance. The frontend consists of five blocks., low noise amplifier,down-converter, up-converter, pre-amplifier, and LO buffer. Their input/output impedance are all on-chip matched to 50 Ω except the down-converter which has open-drain outputs. The transceiver RF front-end has been implemented in a 0. 18μm CMOS process. When the LNA and the down-converter are directly connected, the measured noise figure is 5.2dB, the measured available power gain 12. 5dB, the input l dB compression point --18dBm,and the third-order input intercept point --7dBm. The receiver front-end draws 13.6mA currents from the 1.8V power supply. When the up-converter and pre-amplifier are directly connected, the measured noise figure is 12.4dB, the power gain is 23. 8dB, the output ldB compression point is 1.5dBm, and the third-order output intercept point is 16dBm. The transmitter consumes 27.6mA current from the 1.8V power supply.

Current Mismatches in Charge Pumps of DLL-Based RF CMOS Oscillators

A research on the spurious tones due to the current mismatch in charge pumps of DLL(Delay Locked Loop) based RF CMOS oscillators is performed.An equation for strength evaluation of the spurious tones is derived.Two tables are provided to make it obvious to understand for the characteristics of spurious tones changing with related parameters.Some suggestions are given for the design of a DLL based RF CMOS oscillators.

Design of a Frequency Divider with Reduced Complexity Based on a Resonant Tunneling Diode

A novel edge-triggered D-flip-flop based on a resonant tunneling diode （RTD） is proposed and used to construct a binary frequency divider. The design is discussed in detail and the performance of the circuit is verified using SPICE. Relying on the nonlinear characteristics of RTD,we reduced the number of components used in our DFF circuit to only half of that required using conventional CMOS SCFL technology.

A HIGH PERFORMANCE UWB LFM WAVEFORM GENERATOR

In this paper, the design and implementation of a high performance Ultra-WideBand (UWB) Linear Frequency Modulation (LFM) waveform generator at Very High Frequency/Ultra High Frequency (VHF/UHF) band are introduced. Firstly, the design ideas for a high performance UWB LFM waveform generator are described. Then, a generation scheme for UWB LFM waveforms is presented according to the baseband digital generation method combining with the bandwidth ex-tension method via frequency doubling. An experimental system has been implemented and tested. The results show that the UWB LFM waveform generator achieves very high performance.

A Low-Power,Single-Poly,Non-Volatile Memory for Passive RFID Tags

Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.

Low Power Single-Chip RF Transceiver for Human Body Cormunication

Human body communication is proposed as a promising body proximal comanunication tech- nology for body sensor networks. To achieve low power and slmll volume ill the sensor nodes, a Ra-dio Frequency （RF） application-specific integrated circuit transceiver tbr Human Body Commnunication （HBC） is presented and the characteristics of HBC are investigated. A high data rate On-Off Keying （OOK）/Frequency-Shift Keying （FSK） modulation protocol and an OOK/FSK delrodulator circuit are introduced in this paper, with a data-rate-to-carrier-frequency ratio up to 70%. A low noise amplifier is proposed to handle the dynamic range problem and improve the sensitivity of the receiver path. In addi-tion, a low power autonmatic-gain-control system is realized using a novel architecture, thereby render-ing the peak detector circuit and loop filter unneces-sary. Finally, the complete chip is fabricated. Simula-tion results suggest receiver sensitivity to be-75 dBm. The transceiver shows an overall power con-smxption of 32 mW when data rate is 5 Mbps, de-livering a P1dB output power of - 30 dBm.

IMPROVING THE FREQUENCY RESOLUTION OF DIGITALLY SYNTHESIZED PERIODIC SIGNALS BY A SEQUENTIAL ADDRESSING SCHEME

In the digital synthesis of wideband periodic signals using an Arbitrary Waveform Gen-erator(AWG),the frequency resolution and spectral complexity of the synthesized signals are com-monly limited by the memory capacity and clock frequency of the AWG.This paper proposes a novel sequential addressing scheme and then presents several sequences to improve the frequency resolution of the synthesized periodic signals without changing their spectral envelopes and basic time-domain characteristics under the condition of a fixed memory capacity and a fixed clock fre-quency.The main idea of the scheme is using the address generator in an AWG to program and produce addresses to read fixed waveform data in variable order,and thus to generate waveforms of various periods and profiles.The scheme is applied in simulating signal scenarios for military com-munication countermeasure experiments,and achieves high performance.

A 0.35μm CMOS 6.1GHz 1∶4 Static Frequency Divider

A 1∶4 static frequency divider has been designed and realized in a 0.35-micron standard CMOS technology. The chip consists of two identical 1∶2 divider cells, which are based on SCL (Source Coupled Logic) flip-flops. By revising the traditional topology of SCL flip-flop, we get a divider with better performances. Measurement results show that the whole chip achieves the frequency division at more than 6GHz. Each 1∶2 divider consumes 11mW from a 3.3V supply. The divider can be used in RF and Optic-fiber Transceivers and other high-speed systems.

Third-order active-RC complex filter with automatic frequency tuning for ZigBee transceiver applications

A 3rd-order Butterworth active-RC complex band-pass filter was presented for Zig Bee(IEEE802.15.4) transceiver applications. The filter adopted cascaded complex pole stages to realize the 3 MHz bandwidth with a centre frequency of 2 MHz which was required by the Zig Bee transceiver applications. An automatic frequency tuning scheme was also designed to accommodate the performance deterioration due to the process, voltage and temperature(PVT) variations. The whole filter is implemented in a 0.18 μm standard process and occupies an area of 1.3 mm×0.6 mm. The current dissipation is 1.2 m A from a 1.8 V single power supply. Measurement results show that the image rejection ratio(IRR) of the filter is 24.1 d B with a pass-band ripple less than 0.3 d B. The adjacent channel rejection is 29.8 d B@7 MHz and alternate channel rejection 47.5 d B@12 MHz, respectively.

Clock generator and OOK modulator for RFID application

The clock generator and OOK modulator for RFID (Radio Frequency Identification) presented in this paper consist of a current source and delay elements. The simple constant-gm structure is adopted in the current source design and the current consumption of the current source is only about 2 μA. The delay elements, the clock generator and OOK modulator are introduced in detail in the paper. The designed circuits are fabricated by 0.6 μm CMOS process. The area of the core circuit is only about 400 μm×80 μm. The delay time of all three samples is in the range of 9 μs to 21 μs when the supply voltage varies from 2 V to 4 V. As the measured results satisfy the system requirements, these circuit structures are suitable for RFID application.

Research on DCC Strategy for Grid-Connected Inverter of D-PMSG under Unbalanced Network Voltage Conditions

According to performance analysis of a three-phase grid-connected inverter mathematical model of a directly-driven wind turbine with a permanent magnet synchronous generator (D-PMSG) under unbalanced network voltage conditions, a dual current-loop control strategy (DCC) oriented on positive voltage and negative current is proposed to inhibit the DC voltage fluctuation. Meanwhile, a notch filter is introduced into the conventional control strategy of a phase-locked loop to complete the low voltage ride through (LVRT) ability of the wind generator. A 1.5-MW D-PMSG with a back-to-back IGBT frequency converter was simulated in the PSCAD/EMTDC environment, and simulation results showed that: the maximum wind power tracking was achieved in this system and the proposed DCC strategy could successfully inhibit the rising aging of DC voltage and enhance the ride-through capability of D-PMSG wind generation system under unbalanced network voltage conditions.

Walsh Hadamard Transform Based Transceiver Design for SC-FDMA with Discrete Wavelet Transform

This article proposes a new transceiver design for Single carrier frequency division multiple access(SCFDMA)system based on discrete wavelet transform(DWT). SCFDMA offers almost same structure as Orthogonal frequency division multiple access(OFDMA)with extra advantage of low Peak to Average Power Ratio(PAPR). Moreover,this article also suggests the application of Walsh Hadamard transform(WHT)for linear precoding(LP)to improve the PAPR performance of the system. Supremacy of the proposed transceiver over conventional Fast Fourier transform(FFT)based SCFDMA is shown through simulated results in terms of PAPR,spectral efficiency(SE)and bit error rate(BER).

All-Digital Self-Interference Cancellation in Zero-IF Full-Duplex Transceivers

In this paper,a general scheme in digital self-interference cancellation at baseband for zero-IF full-duplex transceivers is presented. We model the self-interference signals specifically with only the nonlinear distortion signals falling in receiving band considered. A joint estimation algorithm is proposed for compensating the time delay and frequency offset taking into account the IQ amplitude and phase imbalances from mixers. The memory effect and nonlinear distortion are adaptively estimated by the de-correlated normalized least mean square(DNLMS) algorithm. Numerical simulation results demonstrate that the proposed self-interference cancellation scheme can efficiently compensate the self-interference and outperform the existing traditional solutions.