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污水调节池及污水取排系统在污水热能利用中的设计研究 被引量:2
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作者 吴德珠 廖坚卫 +2 位作者 赖文彬 孙德兴 张承虎 《制冷》 2012年第3期66-71,共6页
以污水源热泵系统夏季工况为例,分析了污水调节池体积大小的设计方法。通过介绍污水取、排水口的布置方式和污水取水方式,给出了污水取排系统的设计要点,为污水热能利用工程的设计及施工提供参考。
关键词 污水调节池 取排系统 热泵系统 污水
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Sequencing method for dual-shuttle flow-rack automated storage and retrieval systems 被引量:1
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作者 陈竹西 李小平 《Journal of Southeast University(English Edition)》 EI CAS 2015年第1期31-37,共7页
The dual-retrieval (DR) operation sequencing problem in the flow-rack automated storage and retrieval system (AS/RS) is modeled as an assignment problem since it is equivalent to pairing outgoing unit-loads for ea... The dual-retrieval (DR) operation sequencing problem in the flow-rack automated storage and retrieval system (AS/RS) is modeled as an assignment problem since it is equivalent to pairing outgoing unit-loads for each DR operation. A recursion symmetry Hungarian method (RSHM), modified from the Hungarian method, is proposed for generating a DR operation sequence with minimal total travel time, in which symmetry marking is introduced to ensure a feasible solution and recursion is adopted to break the endless loop caused by the symmetry marking. Simulation experiments are conducted to evaluate the cost effectiveness and the performance of the proposed method. Experimental results illustrate that compared to the single-shuttle machine, the dual-shuttle machine can reduce more than 40% of the total travel time of retrieval operations, and the RSHM saves about 5% to 10% of the total travel time of retrieval operations compared to the greedy-based heuristic. 展开更多
关键词 dual-shuttle SEQUENCING flow rack automatedstorage and retrieval system (AS/RS)
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Performance Behaviour Analysis of the Present 3-Level Cache System for Multi-Core Processors
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作者 Muhammad Ali Ismail 《Computer Technology and Application》 2012年第11期729-733,共5页
In this paper, a study related to the expected performance behaviour of present 3-level cache system for multi-core systems is presented. For this a queuing model for present 3-level cache system for multi-core proces... In this paper, a study related to the expected performance behaviour of present 3-level cache system for multi-core systems is presented. For this a queuing model for present 3-level cache system for multi-core processors is developed and its possible performance has been analyzed with the increase in number of cores. Various important performance parameters like access time and utilization of individual cache at different level and overall average access time of the cache system is determined. Results for up to 1024 cores have been reported in this paper. 展开更多
关键词 MULTI-CORE memory hierarchy cache access time queuing analysis.
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