This paper describes a complete baseband chain for both GSM and WCDMA receivers with a SMIC 0.35μm mixed signal process. The chain consists of a dual-mode,highly linear, fourth order Chebyshev active RC filter and th...This paper describes a complete baseband chain for both GSM and WCDMA receivers with a SMIC 0.35μm mixed signal process. The chain consists of a dual-mode,highly linear, fourth order Chebyshev active RC filter and three VGA stages. The filter is designed to meet the bandwidth specifications of the GSM and WCDMA standards and share the maximum number of components between the two modes to reduce manufacturing cost. The design is free of DC-offset and has an inter-stage high-pass filter, and operational amplifiers with adjustable GBW are used to minimize GSM-mode power consumption. The measured noise figures are 27. 3 and 42dBm in WCDMA and GSM modes,respectively, at the maximum gain. The IIP3 is 40dBm at unit gain in the WCDMA mode,and the circuit consumes 47.0mW. The IIP3 is 28dBm in the GSM mode,and the circuit consumes 31.8mW. The supply voltage is 3.3V.展开更多
文摘This paper describes a complete baseband chain for both GSM and WCDMA receivers with a SMIC 0.35μm mixed signal process. The chain consists of a dual-mode,highly linear, fourth order Chebyshev active RC filter and three VGA stages. The filter is designed to meet the bandwidth specifications of the GSM and WCDMA standards and share the maximum number of components between the two modes to reduce manufacturing cost. The design is free of DC-offset and has an inter-stage high-pass filter, and operational amplifiers with adjustable GBW are used to minimize GSM-mode power consumption. The measured noise figures are 27. 3 and 42dBm in WCDMA and GSM modes,respectively, at the maximum gain. The IIP3 is 40dBm at unit gain in the WCDMA mode,and the circuit consumes 47.0mW. The IIP3 is 28dBm in the GSM mode,and the circuit consumes 31.8mW. The supply voltage is 3.3V.
