无线传感器网络中可容错的事件监测算法

事件监测是传感器网络研究中的一个重要问题,传感器网络自身的局限性以及感知数据的非确定性向事件监测技术提出了挑战.文中分析了传感器网络中存在的各种非确定性,引入可容错的事件监测机制.文中首先提出可容错的事件发现和参与事件监测节点选择算法.在此基础上,提出可容错的事件发生区域估算算法.算法对于动态传感器网络具有较好监测效果.最后通过大量模拟实验验证了所提出算法的性能.

热力系统控制可容错性分析与应用研究

根据系统可控性和可观测性理论 ,通过对控制系统中元 (部 )件冗余性、冗余度的分析 ,研究故障系统可容错的条件 ,对稳压器压力控制系统进行可容错性定量分析 ;通过分析控制系统的部件对系统的静态性能、动态性能的影响程度 ,容错控制系统的部件重要度分析 ,确定引起控制系统故障的关键部件。

新型可容错FPGA

SRAM型FPGA具有设计周期短、开发成本低和可重配置等特性,在大型电子系统设计中应用广泛。伴随SRAM型FPGA在重要领域的深入应用,对其可靠性提出了更高要求。在深入剖析FPGA内部结构的基础上,对SRAM型FPGA的故障类型进行了总结。针对SRAM单元软错误造成的FPGA芯片错误,提出了一种嵌入高可靠CPU和配置存储器,通过重构技术实现在线可修复的新型可容错FPGA结构。

控制系统可容错性分析及应用研究

首先对控制系统的各种故障形式予以分析，给出故障系统的数学模型；然后，提出能控（能观）意义上的功能冗余、系统的能控（能观）冗余度及某个部件对系统的能控（能观）重要度等概念，并对系统的可容错性予以量化分析，从而为控制系统的可靠性设计提供了依据；最后用造纸过程控制系统中的两个实例说明之．

基于混合纠错码的可容错性高速缓存研究

针对低电压下cache硬错误和软错误概率提高导致cache不能正常工作的问题,提出了一种基于混合纠错码的cache结构。该结构利用脏数据正确性必须由处理器中cache保证而干净数据可由片外恢复的数据特征,将cache分成多比特纠错码和单比特纠错码保护的两个区域。通过采用新的cache替换策略,使得脏数据总处于多比特纠错码保护区域,保证其得到较强保护,从而保证cache在低电压下的可靠性运行。基于EEMBC测试基准的实验结果表明,该设计可以在590 m V电压下正常运行,与该领域最新研究VS-ECC相比,降低了23.6%的纠错码存储信息量,性能提高5.9%。

高可扩展可容错的无网格/粒子程序petaPar及其测试

petaPar粒子模拟程序面向千万亿次级计算,在统一框架下实现两种广受关注的粒子模拟算法:光滑粒子流体动力学(Smoothed Particle Hydrodynamics,SPH)和物质点法(Material Point Method,MPM)。代码支持多种材料模型、强度模型和失效模型,适合模拟大变形、高应变率和流固耦合问题。支持纯MPI和MPI+X混合两种并行模型。系统具有可容错性,支持无人值守变进程重启。在Titan上测试表明,petaPar可线性扩展到26万CPU核,SPH和MPM算法并行效率相对8 192核分别为87%和90%。

分布式数据库在金融应用场景中的探索与实践

金融互联网化的迅速发展要求金融数据库系统同时具备高性能、可扩展、高可用和高容错等特性,传统数据库管理系统难以同时满足这些特性。为了应对金融互联网化带来的挑战,响应国家对技术自主可控需求,交通银行专注于支持金融行业典型交易的新一代数据库系统研发,通过实现轻量级分布式选举协议和分布式事务功能,开发了具备高性能、可扩展、高可用和高容错特性的分布式数据库,并成功将其运用于交通银行多个关键业务系统中。

安全高效的群组密钥协商协议

群组密钥协商(GKA)是保证随后安全通信的重要手段之一。提出了一种新的群组密钥协商协议,在协议中,参与者可以通过一系列算法对其他参与者的真伪进行验证。该协议以较低的计算成本实现参与者安全的会话密钥协商,具备可容错性和长期私钥可重用性的特点。分析表明可抵抗多数常见攻击。

STUDY ON MEASURES OF FAULT TOLERANCE FOR DISTRIBUTED SYSTEM

Fault tolerant ability is an important aspect for overall evaluation of distributed system(DS). This paper discusses three measures for the evaluation: node/edge connectivity, number of spanning trees and synthetic connectivity. A numerical example for illustration and analysis is given, and the synthetic connectivity measure presented by this paper is proved to be rational and satisfactory.

A SOLUTION TO HIGH AVAILABILITY OF OPENSTOCK

High availability is a critical mission for business system. At first, an instance of business system OPENSTOCK for pharmacy is introduced including both client and server sides. Secondly, a solution to the high availability of this system is given in detail, including design and implementation. The essentiality of this solution consists of scope of system information, system parameter tables of service status, schedule strategies of load ba lance and how to acquire system parameters and detect service states. The solution proposed is scalable and application oriented and supporting load balance for high performance and fault tolerate for high reliability. This application system has been applied and verified realistically, and the features of this business system derived in this paper have been achieved.

Reliability Analysis of Sensor Networks

To Integrate the capacity of sensing, communication, computing, and actuating, one of the compelling technological advances of these years has been the appearance of distributed wireless sensor network (DSN) for information gathering tasks. In order to save the energy, multi-hop routing between the sensor nodes and the sink node is necessary because of limited resource. In addition, the unpredictable conditional factors make the sensor nodes unreliable. In this paper, the reliability of routing designed for sensor network and some dependability issues of DSN, such as MTTF (mean time to failure) and the probability of connectivity between the sensor nodes and the sink node are analyzed. Unfortunately, we could not obtain the accurate result for the arbitrary network topology, which is #P-hard problem. And the reliability analysis of restricted topologies clustering-based is given. The method proposed in this paper will show us a constructive idea about how to place energy-constrained sensor nodes in the network efficiently from the prospective of reliability.

Early Stage Software Reliability Estimation with Stochastic Reward Nets

This paper presents software reliability modeling issues at the early stage of a software development for fault tolerant software management system. Based on Stochastic Reward Nets, an effective model of hierarchical view for a fault tolerant software management system is put forward, and an approach that consists of system transient performance analysis is adopted. A quantitative approach for software reliability analysis is given. The results show its usefulness for the design and evaluation of the early-stage software reliability modeling when failure data is not available.

Research on the Network Intrusion Detection System based on Modified Particle Swarm Optimization Algorithm

In this paper, we conduct research on the network intrusion detection system based on the modified particle swarm optimization algorithm. Computer interconnection ability put forward the higher requirements for the system reliability design, the need to ensure that the system can support various communication protocols to guarantee the reliability and security of the network. At the same time also require network system, the server or products have strong ability of fault tolerance and redundancy, better meet the needs of users, to ensure the safety of the information data and the good operation of the network system. For this target, we propose the novel paradigm for the enhancement of the modern computer network that is innovative.

A Fault-Tolerant FPGA Architecture

SRAM （Static RAM）-based FPGAs （Field Programmable Gate Arrays （FPGAs） have gained wide acceptance due to their on-line reconfigurable features. The growing demand for FPGAs has motivated semiconductor chip manufacturers to build more densely packed FPGAs with higher logic capacity. The downside of high density devices is that the probability of errors in such devices tends to increase. This paper proposes an FPGA architecture that is composed of an array of cells with built in error correction capability. Collectively a group of such cells can implement any logic function that is either registered or combinational. A cell is composed of three units： a logic block, a fault-tolerant address generator and a director unit. The logic block uses a look-up table to implement logic functions. The fault-tolerant address generator corrects any single bit error in the incoming data to the functional cell. The director block can transmit output data from the logic block to another cell located at its South, North, East or West, or to cells in all four directions. Thus a functional cell can also be used to route signals to other functional cells, thus avoiding any intricate network of interconnects, switching boxes, or routers commonly found in commercially available FPGAs.

Dependability Analysis for Fault-Tolerant Computer Systems Using Dynamic Fault Graphs

Dependability analysis is an important step in designing and analyzing safety computer systems and protection systems.Introducing multi-processor and virtual machine increases the system faults' complexity,diversity and dynamic,in particular for software-induced failures,with an impact on the overall dependability.Moreover,it is very different for safety system to operate successfully at any active phase,since there is a huge difference in failure rate between hardware-induced and softwareinduced failures.To handle these difficulties and achieve accurate dependability evaluation,consistently reflecting the construct it measures,a new formalism derived from dynamic fault graphs(DFG) is developed in this paper.DFG exploits the concept of system event as fault state sequences to represent dynamic behaviors,which allows us to execute probabilistic measures at each timestamp when change occurs.The approach automatically combines the reliability analysis with the system dynamics.In this paper,we describe how to use the proposed methodology drives to the overall system dependability analysis through the phases of modeling,structural discovery and probability analysis,which is also discussed using an example of a virtual computing system.

Low power and high write speed SEU tolerant SRAM data cell design

As feature size scales down, reliability issues like single event upset(SEU) have become serious for circuit and system designers, especially for those who work on memory and latch designs. In this paper, an improved SEU tolerant data cell design based on the Quatro-10 T cell is proposed. The introduced cell enhances the capability of SEU tolerance by weakening the key transistors in the feedback loop to block the effects of transient fault. Simulation results show that our proposed design achieves obvious higher resilience to SEU and better performance on speed and power dissipation at the expense of an increased area. The proposed cell is a fully SEU immune design with an amount of critical charge at least 7 times more than the Quatro-10 T cell and has the lowest Power Delay Product. It shows that our design is very suitable in high-performance circuit and system design.

Design and reliability,availability,maintainability,and safety analysis of a high availability quadruple vital computer system

With the development of high-speed railways in China,more than 2000 high-speed trains will be put into use.Safety and efficiency of railway transportation is increasingly important.We have designed a high availability quadruple vital computer (HAQVC) system based on the analysis of the architecture of the traditional double 2-out-of-2 system and 2-out-of-3 system.The HAQVC system is a system with high availability and safety,with prominent characteristics such as fire-new internal architecture,high efficiency,reliable data interaction mechanism,and operation state change mechanism.The hardware of the vital CPU is based on ARM7 with the real-time embedded safe operation system (ES-OS).The Markov modeling method is designed to evaluate the reliability,availability,maintainability,and safety (RAMS) of the system.In this paper,we demonstrate that the HAQVC system is more reliable than the all voting triple modular redundancy (AVTMR) system and double 2-out-of-2 system.Thus,the design can be used for a specific application system,such as an airplane or high-speed railway system.