New digital drive phase control for improving bias stability of silicon MEMS gyroscope

In order to improve the bias stability of the micro-electro mechanical system（MEMS） gyroscope and reduce the impact on the bias from environmental temperature,a digital signal processing method is described for improving the accuracy of the drive phase in the gyroscope drive mode.Through the principle of bias signal generation,it can be concluded that the deviation of the drive phase is the main factor affecting the bias stability.To fulfill the purpose of precise drive phase control,a digital signal processing circuit based on the field-programmable gate array（FPGA） with the phase-lock closed-loop control method is described and a demodulation method for phase error suppression is given.Compared with the analog circuit,the bias drift is largely reduced in the new digital circuit and the bias stability is improved from 60 to 19 °/h.The new digital control method can greatly increase the drive phase accuracy,and thus improve the bias stability.

APPLICATION AND IMPLEMENTATION OF REAL-TIME IMAGE ZOOMING WITH THE WALSH TECHNIQUE

Based on the study of Walsh transformation,the zooming template of a two dimensional superimposure filter is decomposed and simplified,and it is real time implemented with FPGA.This method is simple and effective.The quality of the image is very good.

New scale factor correction scheme for CORDIC algorithm

To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorithm is proposed. Based on the relationship between the iteration formulae, a new iteration formula is introduced, which leads the correction operation to be several simple shifting and adding operations. As one key part, the effects caused by rounding error are analyzed mathematically and it is concluded that the effects can be degraded by an appropriate selection of coefficients in the iteration formula. The model is then set up in Matlab and coded in Verilog HDL language. The proposed algorithm is also synthesized and verified in field-programmable gate array （FPGA）. The results show that this new scheme requires only one additional clock cycle and there is no change in the elementary iteration for the same precision compared with the conventional algorithm. In addition, the circuit realization is regular and the change in system throughput is very minimal.

Virtual reconfigurable architecture for evolving combinational logic circuits

A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.

Smart Home Based on Wireless Sensor-Actuator Networks

Wireless sensor-actuator networks can bring flexibility to smart home.We design and develop a smart home prototype using wireless sensor-actuator network technology to realize environmental sensing and the control of electric appliances.The basic motivation of our solution is to utilize the collaboration among a mass of low-cost sensor nodes and actuator nodes to make life convenient.To achieve it,we design a novel system architecture with assembled component modules.In particular,we address some key technical challenges:1) Field-Programmable Gate Array (FPGA) Implementation of Adaptive Differential Pulse Code Modulation (ADPCM) for audio data;2) FPGA Implementation of Lempel Ziv Storer Szymanski (LZSS) for bulk data;3) combination of complex control logic.Finally,a set of experiments are presented to evaluate the performance of our solution.

GF-3 data real-time processing method based on multi-satellite distributed data processing system

Due to the limited scenes that synthetic aperture radar(SAR)satellites can detect,the full-track utilization rate is not high.Because of the computing and storage limitation of one satellite,it is difficult to process large amounts of data of spaceborne synthetic aperture radars.It is proposed to use a new method of networked satellite data processing for improving the efficiency of data processing.A multi-satellite distributed SAR real-time processing method based on Chirp Scaling(CS)imaging algorithm is studied in this paper,and a distributed data processing system is built with field programmable gate array(FPGA)chips as the kernel.Different from the traditional CS algorithm processing,the system divides data processing into three stages.The computing tasks are reasonably allocated to different data processing units(i.e.,satellites)in each stage.The method effectively saves computing and storage resources of satellites,improves the utilization rate of a single satellite,and shortens the data processing time.Gaofen-3(GF-3)satellite SAR raw data is processed by the system,with the performance of the method verified.

Design of Parallel Electrical Resistance Tomography System for Measuring Multiphase Flow

ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient hydrodynamics.Aiming at this target,a fully programmable and reconfigurable FPGA(field programmable gate array)-based Compact PCI(peripheral component interconnect) bus linked sixteen-channel ERT system has been presented.The data acquisition system is carefully designed with function modules of signal generator module;Compact PCI transmission module and data processing module(including data sampling,filtering and demodulating).The processing module incorporates a powerful FPGA with Compact PCI bus for communication,and the measurement process management is conducted in FPGA.Image reconstruction algorithms with different speed and accuracy are also coded for this system.The system has been demonstrated in real time(1400 frames per second for 50 kHz excitation) with signal-noise-ratio above 62 dB and repeatability error below 0.7%.Static experiments have been conducted and the images manifested good resolution relative to the actual object distribution.The parallel ERT system has provided alternative experimental platform for the multiphase flow measurements by the dynamic experiments in terms of concentration and velocity.

Towards Wide-Open, Adaptable DCF Implementation for Dynamic Networks

Abstract： This work proposes a Field Programmable Gate Array （FPGA）-oriented architecture for the IEEE 802.11 Distributed Coordination Function （DCF） transceiver. We describe the functional blocks carrying out the Carrier Sense Multiple Accesses with Collision Avoidance （CSMA/CA）, develop the interfaces to the application layer and the physical layer, and implement it on FPGA devices by utilizing Very-high-speed-integrated-circuit Hardware Description Language （VHDL）.

A reconfigurable low-cost memory-efficient VLSI architecture for video scaling

A runtime reconfigurable very-large-scale integration （VLSI） architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a wide range of applications from broadcast, medical imaging and high-resolution video effects to video surveillance, and video conferencing. Many algorithms have been proposed for these applications, such as piecewise polynomial kernels and windowed sinc kernels. The sum of three shifted versions of a B-spline function, whose weights can be adjusted for different applications, is adopted as the main filter. The proposed algorithm is confirmed to be effective on image scaling ap- plications and also verified by many widely acknowledged image quality measures. The reconfigu- rable hardware architecture constitutes an arbitrary scaler with low resource consumption and high performance targeted for field programmable gate array （FPGA） devices. The scaling factor can be changed on-the-fly, and the filter can also be changed during runtime within a unifying framework.

A novel fuzzy logic direct torque controller for a permanent magnet synchronous motor with a field programmable gate array

A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.

Bit-stream linear artificial neural networks based on Sigma-delta modulation

To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural networks （ANN） hardware implementation methods, a bit-stream ANN construction method based on direct sigma-delta （Z-A） signal processing is presented. The bit-stream adder, multiplier and fully digital X-A modulator used in the bit-stream linear ANN are implemented in a field programmable gate array （FPGA）. A bit-stream linear ANN based on these bit-stream modules is presented and implemented. To verify the function and performance of the bit-stream linear ANN, the bit-stream adaptive predictor and the bit-stream adaptive noise cancellation system are presented. The predicted result of the bit-stream adaptive predictor is very close to the desired signal. Also, the bit-stream adaptive noise cancellation system removes the electric power noise effectively.

Research and realization of PWM drive control digitalization for the full digital welding power supply

Pulse width modulation （ PWM） drive control digitalization is the key for the full digital invert power supply. New ideas are proposed, which are based on field programmable gate array （ FPGA ）. First, digital PWM principles are discussed. The primary and secondary current characteristics are analyzed when the transformer is in both normal and magnetic bias conditions. Second, two digitalization methods are put forward after the research on PWM adjustment principles, which are based on the primary current feedback. Though the two methods could restrain magnetic bias, their realization is difficult. A new method is researched on double close-loops to overcome the above shortcomings, which uses the secondary current as the feedback signal and the primary current as the protection signal. Finally, the secondary current control made is discussed and realized. Welding experimental results show that the method has strong flexibility and adaptability, which can be used to realize the full digital welding power supply.

Functional Verification Based on FPGA for AVS Video Decoder

In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles of FPGA verification are introduced.Then,the structure of the FPGA board and the verification methods are illustrated.Finally,the workflow of FPGA verification for audio video coding standard(AVS)decoder and the method of restoring images are introduced in detail.The FPGA resources occupancy is shown and analyzed.The result shows that FPGA can verify the ASIC rapidly and effectively so as to shorten the development cycle.

Electromagnetic emanation exploration in FPGA-based digital design

As semiconductor technologies have been shrinking,the speed of circuits,integration density,and the number of I/O interfaces have been significantly increasing.As a consequence,electromagnetic emanation(EME)becomes a critical issue in digital system designs.Electronic devices must meet electromagnetic compatibility(EMC)requirements to ensure that they operate properly,and safely without interference.I/O buffers consume high currents when they operate.The bonding wires,and lead frames are long enough to play as efficient antennas to radiate electromagnetic interference(EMI).Therefore,I/O switching activities significantly contribute to the EMI.In this paper,we evaluate and analyze the impact of I/O switching activities on the EME.We will change the circuit configurations such as the supply voltage for I/O banks,their switching frequency,driving current,and slew rate.Additionally,a trade-off between the switching frequencies and the number of simultaneous switching outputs(SSOs)is also considered in terms of EME.Moreover,we evaluate the electromagnetic emissions that are associated with the different I/O switching patterns.The results show that the electromagnetic emissions associated I/O switching activities depend strongly on their operating parameters and configurations.All the circuit implementations and measurements are carried out on a Xilinx Spartan-3 FPGA.

A method to improve PUF reliability in FPGAs

Due to the impact of voltage,temperature and device aging,the traditional ring oscillator-based physical unclonable functions(RO-PUF)suffers from a unreliability issue,i.e.,PUF output is subject to a constant change.To improve the reliability of the PUF,a stability test scheme related to the PUF mapping unit is proposed.The scheme uses ring oscillators with multiple complexity and various frequencies as sources of interference,which are placed near the PUF prototype circuit to interfere with it.By identifying and discarding unstable slices whichlead to t e instability of PUF,PUF reliability can be effectively improved.Experimental results show that surrounding logic circuits with multiple complexity and multiple frequencies can identify different unstable slices,a d the higher the complexity,t e more unstable slices are detected.Moreover,compared with newly published PUF literature,t e PUF cicuit possesses better statistical characteristic of randomness and lower resource consumption.W it temperatures varying from 0 to 120 t and voltage fluctuating between 0.85 and 1.2 V,its uniqueness and stability can achieve 49.78%a d 98.00%,respectively,which makes it better for use in t e field of security.

Real-Time Upstream Services Demonstration in Orthogonal Frequency Division Multiplexing- Passive Optical Network System

Abstract： Real-time digital service and mul- timedia service upstream transmission in Dig- ital Signal Processing （DSP）-based Orthogo- nal Frequency Division Multiplexing-Passive Optical Network （OFDM-PON） is experimen- tally demonstrated with Centralised Light Sou- rce （CLS） configuration in this paper. After transmitted over 25 km Standard Single Mode Fibre （SSMF） with -16.5 dBm optical power at receiver, the Bit Error Rate （BER） is 9.5 ×10^-11. The implementations of digital domain up-conversion and down-conversion based on Field Programmable Gate Array （FPGA） are int- roduced, which can reduce the cost of In-ph- ase and Quadrature （IQ） radio frequency mix- ers utilised at transmitter and receiver. A car- rier synchronization algorithm is implemented for compensating carrier offset. A channel eq- ualization algorithm is adopted for compen- sating the damage of channel. A new structure of Frequency Synchronization Unit （FSU） des- igned in FPGA is also proposed to cope with the frequency shifting at receiver.

Application of Remote FPGA Dynamic Reconfiguration System in LED Lighting

The dynamic reconfiguration technique based on field-programmable gate array （FPGA） can improve the resource utilization. Discussed are the dynamic reconfiguration principles and methods. Proposed is a remote dynamic reconfiguration scheme using Xilinx Virtex-Ⅱ FPGA and SMCS Ethernet Physical layer transceiver（PHY）. The hardware of the system is designed with Xilinx Virtex-U XC2V30P FPGA that embedds MicroBlaze and MAC IP core, and its network communication software based on transmission control protoeol/Internet protocol （TCP/IP） protocol is programmed by loading LwIP to MicroBlaze. The experimental results indicate that the remote FPGA dynamic reconfiguration system（RFDRS） can switch freely in the eight lighting modes of light emitting diodes （LED）, and that, using dynamic reconfiguration technology, FPGA resource utilization can be reduced remarkably, which is advantageous in the system upgrade and software update.

Intelligent Camera for Surface Defect Inspection

An intelligent camera for surface defect inspection is presented which can pre-process the surface image of a rolled strip and pick defective areas out at a spead of 1 600 meters per minute. The camera is made up of a high speed line CCD, a 60 Mb/s CCD digitizer with correlated double sampling function, and a field programmable gate array(FPGA), which can quickly distinguish defective areas using a perceptron embedded in FPGA thus the data to be further processed would dramatically be reduced. Some experiments show that the camera can meet high producing speed, and reduce cost and complexity of automation surface inspection systems.

A real-time 5/3 lifting wavelet HD-video de-noising system based on FPGA

In accordance with the application requirements of high definition(HD) video surveillance systems,a real-time 5/3 lifting wavelet HD-video de-noising system is proposed with frame rate conversion(FRC) based on a field-programmable gate array(FPGA),which uses a 3-level pipeline paralleled 5/3 lifting wavelet transformation and reconstruction structure,as well as a fast BayesS hrink adaptive threshold filtering module.The proposed system demonstrates de-noising performance,while also balancing system resources and achieving real-time processing.The experiments show that the proposed system's maximum operating frequency(through logic synthesis and layout using Quartus 13.1 software) can reach 178 MHz,based on the Altera Company's Stratix III EP3SE80 series FPGA.The proposed system can also satisfy real-time de-noising requirements of 1920 × 1080 at60 fps HD-video sources,while also significantly improving the peak signal to noise rate of the denoising images.Compared with similar systems,the system has the advantages of high operating frequency,and the ability to support multiple source formats for real-time processing.

A force feedback master finger in exoskeleton type

In order to eliminate the drawbacks of conventional force feedback gloves, a new type of master fin- ger has been developed. By utilizing three ＂four-bar mechanism joint＂ in series and wire coupling mecha- nism, the master finger transmission ratio is kept exactly 1：1.4：1 in the whole movement range and it can make active motions in both extension and flexion directions. Additionally, to assure faster data transmission and near zero delay in the master-slave operation, a digital signal processing/field programmable gate array （DSP/FPGA-FPGA） structure with 200μs cycle time is designed. The operating modes of the master finger can be contact or non-contact, which depends on the motion states of a slave finger, free motion or constrained motion. The position control employed in non-contact mode ensures unconstrained motion and the force control adopted in contact mode guarantees natural contact sensation. To evaluate the performances of the master finger, an experiment between the master finger and a DLR/HTT dexterous finger is conducted. The results demonstrate that this new type master finger can augment telepresence.