FPGA动态局部可重构技术通常将系统划分为固定模块和可重构模块,可重构模块与其他模块之间的通信都是通过使用特殊的总线宏实现的。总线宏的正确设计是实现FPGA动态局部可重构技术的关键。在研究了FPGA动态局部可重构技术中基于三态缓冲...FPGA动态局部可重构技术通常将系统划分为固定模块和可重构模块,可重构模块与其他模块之间的通信都是通过使用特殊的总线宏实现的。总线宏的正确设计是实现FPGA动态局部可重构技术的关键。在研究了FPGA动态局部可重构技术中基于三态缓冲器(Tri-state Buffer,TBUF)总线宏结构的基础上,采用Xilinx ISE FPGA Editor可视化的方法实现总线宏的设计,并借助可重构硬件平台——XCV800验证板,通过设计动态可重构实验,论证总线宏设计的正确性。展开更多
We design a reconfigurable pipelined multiplier embedded in an FPGA. This design is based on the modified Booth algorithm and performs 18 × 18 signed or 17 × 17 unsigned multiplication. We propose a novel me...We design a reconfigurable pipelined multiplier embedded in an FPGA. This design is based on the modified Booth algorithm and performs 18 × 18 signed or 17 × 17 unsigned multiplication. We propose a novel method for circuit optimization to reduce the number of partial products. A new layout floorplan design of the multiplier block is reported to comply with the constraints imposed by the tile-based FPGA chip design. The multiplier can be configured as synchronous or asynchronous. Its operation can also be configured as pipelined for high-frequency operation. This design can be easily extended for different input and output bit-widths. We employ a novel carry look-ahead adder circuit to generate the final product. The transmission-gate logic is used for the low-level circuits throughout the entire multiplier for fast logic operations. The design of the multiplier block is based on SMIC 0.13μm CMOS technology using full-custom design methodology. The operation of the 18 × 18 multiplier takes 4. lns. The two-stage pipelined operation cycle is 2.5ns. This is 29.1% faster than the commercial multiplier and is 17.5% faster than the multipliers reported in other academic designs. Compared with the distributed LUT-based multiplier,it demonstrates an area efficiency ratio of 33 ： 1.展开更多
文摘FPGA动态局部可重构技术通常将系统划分为固定模块和可重构模块,可重构模块与其他模块之间的通信都是通过使用特殊的总线宏实现的。总线宏的正确设计是实现FPGA动态局部可重构技术的关键。在研究了FPGA动态局部可重构技术中基于三态缓冲器(Tri-state Buffer,TBUF)总线宏结构的基础上,采用Xilinx ISE FPGA Editor可视化的方法实现总线宏的设计,并借助可重构硬件平台——XCV800验证板,通过设计动态可重构实验,论证总线宏设计的正确性。
文摘We design a reconfigurable pipelined multiplier embedded in an FPGA. This design is based on the modified Booth algorithm and performs 18 × 18 signed or 17 × 17 unsigned multiplication. We propose a novel method for circuit optimization to reduce the number of partial products. A new layout floorplan design of the multiplier block is reported to comply with the constraints imposed by the tile-based FPGA chip design. The multiplier can be configured as synchronous or asynchronous. Its operation can also be configured as pipelined for high-frequency operation. This design can be easily extended for different input and output bit-widths. We employ a novel carry look-ahead adder circuit to generate the final product. The transmission-gate logic is used for the low-level circuits throughout the entire multiplier for fast logic operations. The design of the multiplier block is based on SMIC 0.13μm CMOS technology using full-custom design methodology. The operation of the 18 × 18 multiplier takes 4. lns. The two-stage pipelined operation cycle is 2.5ns. This is 29.1% faster than the commercial multiplier and is 17.5% faster than the multipliers reported in other academic designs. Compared with the distributed LUT-based multiplier,it demonstrates an area efficiency ratio of 33 ： 1.
