A low-power 14-bit 150MS/s an- alog-to-digital converter (ADC) is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor shari...A low-power 14-bit 150MS/s an- alog-to-digital converter (ADC) is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier (SHA) is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.展开更多
文摘诸如交通网络、供水网络、电信网络、燃气网络等在人们的生活中极其重要,但是这些网络容易受到自然和人为等因素的影响导致失效,进而降低其连通性。为研究其连通性问题,改进SCM(sequential compounding method)实现了考虑点和线可靠性的有向无环网络连通性的计算方法。该算法是一种快速可靠性评价算法,其结果是近似的,适用于分析可分解为点—线—点结构的网络,特别适用于有一定统计规律的网络。算法主要由两种运算组成,即"与"合并和"或"合并,通过这两种运算将网络化简直到合并为一个点为止。计算八种典型的网络,并将结果与文献和MCS(Monte Carlo simulations)比较,结果表明,提出的算法与MCS相比计算得到的连通性略有不同,误差在-6.2%~4.6%;但是计算时间差别很大,大约是MCS的1.2%~9.2%。
基金supported by the Major National Science & Technology Program of China under Grant No.2012ZX03004004-002National High Technology Research and Development Program of China under Grant No. 2013AA014302
文摘A low-power 14-bit 150MS/s an- alog-to-digital converter (ADC) is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier (SHA) is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.