似曾相识——经典电影音乐合辑

在看电影的时候，无意间，有时会突然听到古典音乐旋律。那就好像在异乡偶遇故人的险，既亲切又陌生。也许，可以随着旋律哼哼几句，或者说得出作曲者的名字，甚至更绝妙一些，按着旋律和剧情的相合，生出“果然恰如其分”的认知，那真有他乡遇故知的喜悦了。

Array-enhanced Logical Stochastic Resonance in Coupled Bistable Systems

We investigate the impact of coupling on the reliability of the logic system as well as the logical stochastic resonance （LSR） phenomenon in the coupled logic gates system. It is found that compared with single logic gate, the coupled system could yield reliable logic outputs in a much wider noise region, which means coupling can obviously improve the reliability of the logic system and thus enhance the LSR effect. Moreover, we find that the enhancement is larger for larger system size, whereas for large enough size the enhancement seems to be saturated. Finally, we also examine the effect of coupling strength, it can be observed that the noise region where reliable logic outputs can be obtained evolves non-monotonically as the coupling strength increases, displaying a resonance-like effect.

《吕氏春秋》的历史超越精神

《吕氏春秋》一书体现了主编者吕不韦不满秦王暴政和法家理论的偏颇，要求改革政治、丰富秦国文化的进步思想。该书对战国以来的诸子百家之学进行了全面的继承。它摒弃门户之见，对各派的学术成果兼收并畜、博采众长并形成了“杂家”自身的体系和特色。

A General Method in the Synthesis of Ternary Double Pass-Transistor Circuits

A general method for designing ternary circuits using double pass-transistor logic is investigated. The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effective and practical use of the circuits. A way to generate ternary complementary and dual circuits by applying the complementarity and duality principles is presented. This new static ternary double pass-transistor logic scheme has some favorable properties：the use of standard CMOS process without any modification of the thresholds, a perfectly symmetrical structure,a full logic swing, the maximum possible noise margins, a less complex structure, and no static power consumption. HSPICE simulations using TSMC 0.25μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design.

Static CMOS Implementation of Logarithmic Skip Adder

Circuit design of 32 bit logarithmic skip adder (LSA) is introduced to implement high performance,low power addition.ELM carry lookahead adder is included into groups of carry skip adder and the hybrid structure costs 30% less hardware than ELM.At circuit level,a carry incorporating structure to include the primary carry input in carry chain and an 'and xor' structure to implement final sum logic in 32 bit LSA are designed for better optimization.For 5V,1μm process,32 bit LSA has a critical delay of 5 9ns and costs an area of 0 62mm 2,power consumption of 23mW at 100MHz.For 2 5V,0 25μm process,critical delay of 0 8ns,power dissipation of 5 2mW at 100MHz is simulated.

原声电影

《当真爱来敲门》(Bounce) 本张电影原声带的音乐总监Randall Poster此番为《当真爱来敲门》选择歌曲时,企图从歌者轻柔歌声或旋律编曲本身,捕捉一些梦呓般意境的律动来丰润不一样的爱情时尚酷感。1999年以“Kiss ME”

Study of Controlling Clutch Engagement for AMT Based on Fuzzy Logic

The control of the clutch engagement for an automatic mechanical transmission in the process of a tracklayer getting to start is studied. The dynamic model of power transmission and automatic clutch system is developed. Using tools of Simulink, the transient characteristics during the vehicle starting, including the jerk and the clutch slip time, are provided here. Based on the analyses of the simulation results and driver’s experiences, a fuzzy controller is designed to control the clutch engagement. Simulation results verify its value.

Modeling and Control of a Continuous Stirred Tank Reactor Based on a Mixed Logical Dynamical Model

A novel control strategy for a continuous stirred tank reactor(CSTR)system,which has the typical characteristic of strongly pronounced nonlinearity,multiple operating points,and a wide operating range,is initiated from the point of hybrid systems.The proposed scheme makes full use of the modeling power of mixed logical dy- namical(MLD)systems to describe the highly nonlinear dynamics and multiple operating points in a unified framework as a hybrid system,and takes advantage of the good control quality of model predictive control(MPC) to design a controller.Thus,this approach avoids oscillation during switching between sub-systems,helps to relieve shaking in transition,and augments the stability robustness of the whole system,and finally achieves optimal(i.e. fast and smooth)transition between operating points.The simulation results demonstrate that the presented ap- proach has a satisfactory performance.

State Feedback Predictive Control for Hybrid System via Parametric Optimization

In this article, state feedback predictive controller for hybrid system via parametric programming is proposed. First, mixed logic dynamic （MLD） modeling mechanism for hybrid system is analyzed, which has a distinguished advantage to deal with the logic rules and constraints of a plant. Model predictive control algorithm with moving horizon state estimator （MHE） is presented. The estimator is adopted to estimate the current state of the plant with process disturbance and measurement noise, and the state estimated are utilized in the predictive controller for both regulation and tracking problems of the hybrid system based on MLD model. Off-line parametric programming is adopted and then on-line mixed integer programming problem can be treated as the parameter programming with estimated state as the parameters. A three tank system is used for computer simulation, results show that the proposed MHE based predictive control via parametric programming is effective for hybrid system with model/olant mismatch, and has a potential for the engineering applications.

Virtual reconfigurable architecture for evolving combinational logic circuits

A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.

Energy Recovery Capacitance Coupling Logic and Its Synthesis Methodology

A novel energy recovery logic style ERCCL （energy recovery capacitance coupling logic） , which has good energy performance compared to the conventional CMOS logic and other advanced energy recovery logic, is proposed. ERCCL uses capacitance coupling to perform a logic function, so it can energy-efficiently implement a high fan-in complex logic in a single gate. ERCCL is also a type of threshold logic. The gate count of a system based on ERCCL can be significantly reduced,which,in turn,will decrease the energy loss. A threshold logic synthesis methodology for ERCCL is also presented. MCNC benchmarks are run through the proposed synthesis methodology. The results indicate that about an 80% reduction in gate count can be obtained when compared with the synthesis results of SIS.

POWER OPTIMIZATION ALGORITHM BASED ON XNOR/OR LOGIC

Based on the investigation of the XNOR/OR logical expression and the propagation al- gorithm of signal probability, a low power synthesis algorithm based on the XNOR/OR logic is pro- posed in this paper. The proposed algorithm has been implemented with C language. Fourteen Mi- croelectronics Center North Carolina (MCNC) benchmarks are tested, and the results show that the proposed algorithm not only significantly reduces the average power consumption up to 27% without area and delay compensations, but also makes the runtime shorter.

Graph Clustering Algorithm for RT Level ALU Technology Mapping

Register transfer level mapping (RTLM) algorithm for technology mapping at RT level is presented,which supports current design methodologies using high level design and design reuse.The mapping rules implement a source ALU using target ALU.The source ALUs and the target ALUs are all represented by the general ALUs and the mapping rules are applied in the algorithm.The mapping rules are described in a table fashion.The graph clustering algorithm is a branch and bound algorithm based on the graph formulation of the mapping algorithm.The mapping algorithm suits well mapping of regularly structured data path.Comparisons are made between the experimental results generated by 1 greedy algorithm and graphclustering algorithm,showing the feasibility of presented algorithm.

New autocorrelation topological indexes and their application in QSAR study

Considering the problems of classical structure parameters that existed in the study of quantitative structure activity relationship (QSAR). Two new groups of autocorrelation topological indexes V(t), E(t), (P(t)) and A(t), B(t), C(t), D(t) were developed on the basis of molecular topology and autocorrelation function in mathematics. The first group were obtained from Van der Waals volume, electronegativity and topological vertex degree;and the second group were obtained from the different combination of topological vertex degree.Corresponding softwares of ATIJP and ATITP have been developed for calculating these two new groups of indexes. Better results have been obtained from the application of these indexes in QSAR study.

A DELTA INFERENCE OPERATOR FOR REASONABLE CONSEQUENCE RELATION

This paper determines a delta inference operator C based on the notion of reasonable consequence of Adams′ system and studies its properties. It shows another approach to study inductive and probabilistic reasoning.

Belief and Knowledge Reasoning

Alternating-time Temporal Epistemic Logic (ATEL) which is an important kind of multi-agent cooperation logics only takes knowledge into account,but does not deal with belief of agents. By introducing three kinds of belief operators into ATEL,a new multi-agent cooperation logic named ATBKL (Alternating-time Temporal Belief and Knowledge Logic) was developed. A model checking algorithm was proposed. It is proved that the model checking complexity of ATBKL is the same as that of ATEL,i.e.,the presented logic is better for further study of multi-agent systems.

Enhanced Side-Channel Leakage Detection Method by Considering Combinational Logic

In this paper,we propose a hybrid power model that includes the power consumption of not only the registers but also part of the combinational logic.By doing knownkey analysis with this hybrid model,power side-channel leakage caused by correct keys can be detected.In experiment,PRINTcipher and DES algorithms were chosen as analysis targets and combinational logic s-box unit was selected to build power template.The analysis results showed the signal-to-noise ratio(SNR) power consumption increase of more than 20%after considering s-box's power consumption so that the information of keys can be obtained with just half number of power traces.In addition,the side channel-leakage detection capability of our method also shows better effectiveness that can identify the correct keys.

A weighted averaging method for signal probability of logic circuit combined with reconvergent fan-out structures

By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failure probability of the gate,first,the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal convergence.Secondly,the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability calculation.Then,the weighted signal probability was calculated by combining the weighted average approach to correct the signal probability.Finally,the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the accuracy.Simulation results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate,and its accuracy is 4.2%higher than that of the IWAA.

Multi-agent Belief,Goal and Exceptions Reasoning

Temporal logics are often adopted as basic tools to specifying mental states such as belief and goal of agents. Although there are works on non-monotonic extension of linear temporal logic (LTL) and branching time temporal logic (CTL),the non-monotonic extension of alternating-time temporal logic (ATL) which is an important kind of multi-agent cooperation logics has not been discussed yet in literature. To solve this problem,this paper proposed non-monotonic alternating-time temporal logic with belief and goal,namely N-ATL-BG,to facilitate the non-monotonic reasoning of mental states of agents. The semantic model,syntax and semantics of this new logic are developed. A model checking algorithm which can be finished in polynomial time is proposed for this new logic. Examples are given to show its usage.

A Combinational Power Analysis Method against Cryptographic Hardware

Power analysis is a non-invaslve attack against cryptographic hardware, which effectively exploits runtime power consumption characteristics of circuits. This paper proposes a new power model which combines Hamming Distance model and the model based on the template value of power consumption in combinational logic circuit. The new model can describe the power consumption characteristics of sequential logic circuits and those of combinational logic as well. The new model can be used to improve the existing power analysis methods and detect the information leakage of power consumption. Experimental results show that, compared to CPA（Correlation Power Analysis） method, our proposed attack which adopt the combinational model is more efficient in terms of the number of required power traces.