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基于计算机仿真技术掩膜圆晶片的电镀工艺模拟 被引量:2
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作者 裴芳 《热加工工艺》 CSCD 北大核心 2013年第18期119-121,共3页
针对传统掩膜圆晶片存在的电镀工艺不完善和电镀质量差等问题,本文结合实际掩膜圆晶片电镀工艺,基于计算机仿真技术,模拟了在掩膜圆晶片上镀铜的瞬态电镀工艺。电镀仿真结果表明,通过电流采集器的添加,使铜电镀镀层厚度变得更加均匀,并... 针对传统掩膜圆晶片存在的电镀工艺不完善和电镀质量差等问题,本文结合实际掩膜圆晶片电镀工艺,基于计算机仿真技术,模拟了在掩膜圆晶片上镀铜的瞬态电镀工艺。电镀仿真结果表明,通过电流采集器的添加,使铜电镀镀层厚度变得更加均匀,并且随着镀层的加厚,镀层的阻抗损耗减小,从而得到具有均匀厚度分布的掩膜圆晶片电镀工艺。 展开更多
关键词 掩膜圆晶片 计算机仿真技术 电镀工艺 模拟
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基于SoC测试系统的RF圆晶片测试技术
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作者 Advantest Corporation, Advantest(Suzhou) Co., Ltd Suzhou 215021,China 《电子工业专用设备》 2009年第3期15-19,共5页
以手机为代表的无线通信应用技术已向SiP化发展,因此对构成SiP芯片的各个单元(chip)进行圆晶片级别的测试就必不可少。爱德万测试(ADVANTEST)开发了基于SoC测试系统的RF圆晶片测试解决方案,提供了一系列新技术来解决串扰、电源阻抗和等... 以手机为代表的无线通信应用技术已向SiP化发展,因此对构成SiP芯片的各个单元(chip)进行圆晶片级别的测试就必不可少。爱德万测试(ADVANTEST)开发了基于SoC测试系统的RF圆晶片测试解决方案,提供了一系列新技术来解决串扰、电源阻抗和等长布线等课题,从而实现低成本的圆晶片测试。本文将就RF圆晶片级别测试技术及SoC测试系统来介绍该RF圆晶片测试方案。 展开更多
关键词 RF 圆晶片测试 SOC测试系统 串扰 同测 低成本
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Drop failure modes of Sn-3.0Ag-0.5Cu solder joints in wafer level chip scale package 被引量:5
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作者 黄明亮 赵宁 +1 位作者 刘爽 何宜谦 《Transactions of Nonferrous Metals Society of China》 SCIE EI CAS CSCD 2016年第6期1663-1669,共7页
To reveal the drop failure modes of the wafer level chip scale packages (WLCSPs) with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were iden... To reveal the drop failure modes of the wafer level chip scale packages (WLCSPs) with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board (PCB) side, split between redistribution layer (RDL) and Cu under bump metallization (UBM), RDL fracture, bulk cracks and partial bulk and intermetallic compound (IMC) cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side. 展开更多
关键词 Sn-3.0Ag-0.5Cu wafer level chip scale package solder joint drop failure mode
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新闻
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《电子设计应用》 2004年第6期80-81,共2页
关键词 法国原子能委员会 CEA Crolles2联盟 圆晶片 英特尔公司 双内核处理器
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Precise Control of Temperature Rising Speed of Wafer during Rapid Thermal Processing
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作者 Shigeki Hirasawa Tsuyoshi Kawanami Katsuaki Shirai Tetsuya Urimoto Naoki Morimoto Atsushi Fujiwara Sadanori Toda 《Journal of Mechanics Engineering and Automation》 2014年第5期359-364,共6页
In rapid thermal processing of a semiconductor wafer, it is important to keep a given temperature rising speed of the wafer during the temperature rising process. We made an experimental apparatus to measure the tempe... In rapid thermal processing of a semiconductor wafer, it is important to keep a given temperature rising speed of the wafer during the temperature rising process. We made an experimental apparatus to measure the temperature rising speed of a ceramic ball of 2 mm in diameter heated with four halogen lamp heaters. The heating rate of the halogen lamp heaters was controlled by computer to keep a given temperature rising speed of 50 ℃/s with a controlling time interval of 0.1 s. We examined the effect of various heating control methods on the error of the temperature rising speed of the ceramic ball. We found that a combined method of control with prepared correlation and PID (proportional integral derivative) control is a good method to decrease the error of the temperature rising speed. The average error of the temperature rising speed is 0.5 ℃/s, and the repetition error is almost zero for the temperature rising speed of 50 ℃/s from 330 ℃ to 370 ℃. We also measured the effects of artificial control delay time and measuring error of the monitoring temperature on the error of the temperature rising speed. 展开更多
关键词 Electronic equipment manufacturing rapid heating heat treatment temperature control PID control.
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