晶体管场环终端技术的优化设计及应用

主要研究晶体管中浮空场环的技术原理和设计优化及其在实际应用中对晶体管耐压性能的影响。在实际产品版图设计中采用了浮空场环设计并通过优化场环间距来满足晶体管的高耐压要求,并通过Silvaco软件进行工艺和器件仿真。根据仿真结果及理论计算进行浮空场环优化设计,并通过实际流片验证浮空场环对晶体管耐压性能的提高效果。

A New Quasi 2-Dimensional Analytical Approach to Predicting Ring Junction Voltage,Edge Peak Fields and Optimal Spacing of Planar Junction with Single Floating Field Limiting Ring Structure

WT8.BZ]A new quasi 2-dimensional analytical approach to predicting the ring voltage,edge peak fields and optimal spacing of the planar junction with a single floating field limiting ring structure has been proposed,based on the cylindrical symmetric solution and the critical field concept.The effects of the spacing and reverse voltage on the ring junction voltage and edge peak field profiles have been analyzed.The optimal spacing and the maximum breakdown voltage of the structure have also been obtained.The analytical results are in excellent agreement with that obtained from the 2-D device simulator,MEDICI and the reported result,which proves the presented model valid.

600V 4H-SiC p+槽VDMOS雪崩耐量的仿真分析

本文为了优化4H-Si CVDMOS的雪崩耐量,提出了一种新型的p^(+)槽和深p^(+)结合的4H-Si CVDMOS,利用TCAD仿真揭示了第一个场限环间距、p^(+)槽的尺寸和深p^(+)区的掺杂分布对VDMOS击穿和非箝位感性开关特性的影响规律。仿真结果表明,与传统结构相比,本文介绍的p^(+)槽VDMOS第一根环间距小于1.3μm、p^(+)区结深大于1.1μm、峰值浓度为5×10^(19)cm^(-3)±20%时,击穿位置由主结转移到有源区p^(+)拐角处,雪崩耐量密度提高了6.1J/cm^(2)。