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一种适用于开关电容电路的MOS开关栅增压电路
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作者 张剑云 李建 +2 位作者 郭亚炜 沈泊 张卫 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2005年第9期1808-1812,共5页
提出了一种新的MOS器件栅增压电路,它在减小MOS开关导通电阻的同时,减少了衬偏效应以及MOS开关输出信号的失真.该电路采用了0.13μm1.2V/2.5VCMOS工艺,HSPICE的仿真结果表明该栅增压电路适用于高速低电压开关电容电路.
关键词 开关 导通 MOS开关 增压电路
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A monolithic InGaP/GaAs HBT power amplifier for W-CDMA applications 被引量:1
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作者 黄继伟 王志功 +2 位作者 廖英豪 陈志坚 方志坚 《Journal of Southeast University(English Edition)》 EI CAS 2011年第2期132-135,共4页
A monolithic microwave integrated circuit (MMIC) power amplifier (PA) is proposed. It adopts a new on-chip bias circuit, which not only avoids the instability of the direct current bias caused by the change in the... A monolithic microwave integrated circuit (MMIC) power amplifier (PA) is proposed. It adopts a new on-chip bias circuit, which not only avoids the instability of the direct current bias caused by the change in the power supply and temperature, but also compensates deviations caused by the increase in input power. The bias circuit is a current-mirror configuration, and the feedback circuit helps to maintain bias voltage at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit. A shunt capacitor at the base node of the active bias transistor enhances the linearity of the PA. The chip is fabricated in an InGaP/GaAs heterojunction bipolar transistor (HBT) process. Measured results exhibit a 26. 6-dBm output compression point, 33.6% power-added efficiency (PAE) and - 40.2 dBc adjacent channel power ratio (ACPR) for wide-band code division multiple access (W-CDMA) applications. 展开更多
关键词 power amplifier wide-band code division multipleaccess(W-CDMA) heterojunction bipolar transistor (HBT) bias circuit gain compression
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视听产品
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《消费电子》 2003年第12期70-70,共1页
关键词 便携式 输入输出 红外线遥控器 卫星接收天线 播放器 增压电路 防震保护 旋转屏幕 液晶屏 卫星
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CMOS low-dropout regulator with 3.3 μA quiescent current without off-chip capacitor
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作者 王忆 崔传荣 +1 位作者 巩文超 何乐年 《Journal of Southeast University(English Edition)》 EI CAS 2009年第1期13-17,共5页
A CMOS (complementary metal-oxide-semiconductor transistor) low-dropout regulator (LDO) with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins ... A CMOS (complementary metal-oxide-semiconductor transistor) low-dropout regulator (LDO) with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement(SRE) circuit and nested Miller compensation (NMC) on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results. 展开更多
关键词 low-dropout regulator off-chip capacitor slew-rate enhancement circuit nested Miller compensation(NMC)
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