A monolithic microwave integrated circuit （MMIC） power amplifier （PA） is proposed. It adopts a new on-chip bias circuit, which not only avoids the instability of the direct current bias caused by the change in the...A monolithic microwave integrated circuit （MMIC） power amplifier （PA） is proposed. It adopts a new on-chip bias circuit, which not only avoids the instability of the direct current bias caused by the change in the power supply and temperature, but also compensates deviations caused by the increase in input power. The bias circuit is a current-mirror configuration, and the feedback circuit helps to maintain bias voltage at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit. A shunt capacitor at the base node of the active bias transistor enhances the linearity of the PA. The chip is fabricated in an InGaP/GaAs heterojunction bipolar transistor （HBT） process. Measured results exhibit a 26. 6-dBm output compression point, 33.6% power-added efficiency （PAE） and - 40.2 dBc adjacent channel power ratio （ACPR） for wide-band code division multiple access （W-CDMA） applications.展开更多
With the large-signal model extracted from the InGaP/GaAs HBT with three fingers,a three-stage,class AB power amplifier at ISM band is designed.Through the optimization of the traditional bias network,the gain compres...With the large-signal model extracted from the InGaP/GaAs HBT with three fingers,a three-stage,class AB power amplifier at ISM band is designed.Through the optimization of the traditional bias network,the gain compression at the low input power level is eliminated successfully.At 3.5V of supply voltage of the power amplifier after optimization exhibits 30dBm of maximum linear output power,43.4% of power added efficiency 109.7mA of a quite low quiescent bias current ,29.1dB of the corresponding gain,and -100dBc of the adjacent channel power rejection (ACPR) at the output power of 30dBm.展开更多
This paper describes a complete baseband chain for both GSM and WCDMA receivers with a SMIC 0.35μm mixed signal process. The chain consists of a dual-mode,highly linear, fourth order Chebyshev active RC filter and th...This paper describes a complete baseband chain for both GSM and WCDMA receivers with a SMIC 0.35μm mixed signal process. The chain consists of a dual-mode,highly linear, fourth order Chebyshev active RC filter and three VGA stages. The filter is designed to meet the bandwidth specifications of the GSM and WCDMA standards and share the maximum number of components between the two modes to reduce manufacturing cost. The design is free of DC-offset and has an inter-stage high-pass filter, and operational amplifiers with adjustable GBW are used to minimize GSM-mode power consumption. The measured noise figures are 27. 3 and 42dBm in WCDMA and GSM modes,respectively, at the maximum gain. The IIP3 is 40dBm at unit gain in the WCDMA mode,and the circuit consumes 47.0mW. The IIP3 is 28dBm in the GSM mode,and the circuit consumes 31.8mW. The supply voltage is 3.3V.展开更多
基金The National High Technology Research and Development Program of China(863 Program)(No.2009AA01Z260)
文摘A monolithic microwave integrated circuit （MMIC） power amplifier （PA） is proposed. It adopts a new on-chip bias circuit, which not only avoids the instability of the direct current bias caused by the change in the power supply and temperature, but also compensates deviations caused by the increase in input power. The bias circuit is a current-mirror configuration, and the feedback circuit helps to maintain bias voltage at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit. A shunt capacitor at the base node of the active bias transistor enhances the linearity of the PA. The chip is fabricated in an InGaP/GaAs heterojunction bipolar transistor （HBT） process. Measured results exhibit a 26. 6-dBm output compression point, 33.6% power-added efficiency （PAE） and - 40.2 dBc adjacent channel power ratio （ACPR） for wide-band code division multiple access （W-CDMA） applications.
文摘With the large-signal model extracted from the InGaP/GaAs HBT with three fingers,a three-stage,class AB power amplifier at ISM band is designed.Through the optimization of the traditional bias network,the gain compression at the low input power level is eliminated successfully.At 3.5V of supply voltage of the power amplifier after optimization exhibits 30dBm of maximum linear output power,43.4% of power added efficiency 109.7mA of a quite low quiescent bias current ,29.1dB of the corresponding gain,and -100dBc of the adjacent channel power rejection (ACPR) at the output power of 30dBm.
文摘This paper describes a complete baseband chain for both GSM and WCDMA receivers with a SMIC 0.35μm mixed signal process. The chain consists of a dual-mode,highly linear, fourth order Chebyshev active RC filter and three VGA stages. The filter is designed to meet the bandwidth specifications of the GSM and WCDMA standards and share the maximum number of components between the two modes to reduce manufacturing cost. The design is free of DC-offset and has an inter-stage high-pass filter, and operational amplifiers with adjustable GBW are used to minimize GSM-mode power consumption. The measured noise figures are 27. 3 and 42dBm in WCDMA and GSM modes,respectively, at the maximum gain. The IIP3 is 40dBm at unit gain in the WCDMA mode,and the circuit consumes 47.0mW. The IIP3 is 28dBm in the GSM mode,and the circuit consumes 31.8mW. The supply voltage is 3.3V.
