采用big.LITTLE技术的ARM架构已经成为高效能处理器领域的热点研究对象,文章基于遗传基因算法设计了一种功耗感知的实时任务调度算法。算法基于动态电压频率调整技术(Dynamic Voltage and Frequency Scaling,DVFS)动态调整处理器电压以...采用big.LITTLE技术的ARM架构已经成为高效能处理器领域的热点研究对象,文章基于遗传基因算法设计了一种功耗感知的实时任务调度算法。算法基于动态电压频率调整技术(Dynamic Voltage and Frequency Scaling,DVFS)动态调整处理器电压以控制处理器动态功耗,在已知任务执行开销和通信开销的情况下实现功耗优化的实时任务调度。利用伪随机任务图生成器(Task Graphs for Free,TGFF)进行了Benchmark实验,实验结果表明,与现有调度算法相比,新算法在满足任务的完成时间约束下平均降低30%的处理器功耗。展开更多
In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware m...In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.展开更多
文摘采用big.LITTLE技术的ARM架构已经成为高效能处理器领域的热点研究对象,文章基于遗传基因算法设计了一种功耗感知的实时任务调度算法。算法基于动态电压频率调整技术(Dynamic Voltage and Frequency Scaling,DVFS)动态调整处理器电压以控制处理器动态功耗,在已知任务执行开销和通信开销的情况下实现功耗优化的实时任务调度。利用伪随机任务图生成器(Task Graphs for Free,TGFF)进行了Benchmark实验,实验结果表明,与现有调度算法相比,新算法在满足任务的完成时间约束下平均降低30%的处理器功耗。
基金supported partially by the National High Technical Research and Development Program of China (863 Program) under Grants No. 2011AA040101, No. 2008AA01Z134the National Natural Science Foundation of China under Grants No. 61003251, No. 61172049, No. 61173150+2 种基金the Doctoral Fund of Ministry of Education of China under Grant No. 20100006110015Beijing Municipal Natural Science Foundation under Grant No. Z111100054011078the 2012 Ladder Plan Project of Beijing Key Laboratory of Knowledge Engineering for Materials Science under Grant No. Z121101002812005
文摘In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.
