Linear transceiver designs are investigated for distributed two-way relaying networks,which aim at minimising the WeightedMean Square Error(WMSE) of data detections.The forwarding matrices at relays andequalization ma...Linear transceiver designs are investigated for distributed two-way relaying networks,which aim at minimising the WeightedMean Square Error(WMSE) of data detections.The forwarding matrices at relays andequalization matrices at destinations are jointly optimised.To overcome the challenginglimitations introduced by individual powerconstraints,a Semi-Definite Relaxation(SDR)called element-wise relaxation is proposed,which can transform the original optimizationproblem into a standard convex optimizationproblem.In this research,two-way relaying isunderstood from a pure signal processing perspective which can potentially simplify thetheoretical analysis.Finally,simulation resultsare used for assessing the performance advantage of the proposed algorithm.展开更多
The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network...The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network packet processing to get high programmability and reduce the time-to-market. However,there is a great gap between the packet processing performance of commodity multi-core and that of the traditional packet processing hardware, e.g., NP(Network Process). Recently, optimization of the packet processing performance of commodity multi-cores has become a hot topic in industry and academia. In this paper, based on a detailed analysis of the packet processing procedure, firstly we identify two dominating overheads, namely the virtual-to-physical address translation and the packet buffer management. Secondly, we make a comprehensive survey on the current optimization methods. Thirdly, based on the survey, the heterogeneous architecture of the commodity multi-core + FPGA is proposed as a promising way to improve the packet processing performance.Fourthly, a novel Self-Described Buffer(SDB) management technology is introduced to eliminate the overheads of the allocation and deallocation of the packet buffers offloaded to FPGA. Then, an evaluation testbed, named PIOT(Packet I/O Testbed), is designed and implemented to evaluate the packet forwarding performance. I/O capacity of different commodity multi-core CPUs and the performance of optimization methods are assessed and compared based on PIOT. At last, the future work of packet processing optimization on multi-core CPUs is discussed.展开更多
基金supported in part by EricssonNational Science and Technology Major Project under Grant No.2010ZX03003-003-03+2 种基金Sino-Swedish IMT-Advanced and Beyond Cooperative Program under Grant No.2008DFA11780National Natural Science Foundation of China under Grant No.61101130the Excellent Young Scholar Research Funding of Beijing Institute of Technology under Grant No.2013CX04038
文摘Linear transceiver designs are investigated for distributed two-way relaying networks,which aim at minimising the WeightedMean Square Error(WMSE) of data detections.The forwarding matrices at relays andequalization matrices at destinations are jointly optimised.To overcome the challenginglimitations introduced by individual powerconstraints,a Semi-Definite Relaxation(SDR)called element-wise relaxation is proposed,which can transform the original optimizationproblem into a standard convex optimizationproblem.In this research,two-way relaying isunderstood from a pure signal processing perspective which can potentially simplify thetheoretical analysis.Finally,simulation resultsare used for assessing the performance advantage of the proposed algorithm.
基金supported by National High-tech R&D Program of China(863 Program)(Grant No.2015AA0156-03)National Natural Science Foundation of China(Grant No.61202483)
文摘The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network packet processing to get high programmability and reduce the time-to-market. However,there is a great gap between the packet processing performance of commodity multi-core and that of the traditional packet processing hardware, e.g., NP(Network Process). Recently, optimization of the packet processing performance of commodity multi-cores has become a hot topic in industry and academia. In this paper, based on a detailed analysis of the packet processing procedure, firstly we identify two dominating overheads, namely the virtual-to-physical address translation and the packet buffer management. Secondly, we make a comprehensive survey on the current optimization methods. Thirdly, based on the survey, the heterogeneous architecture of the commodity multi-core + FPGA is proposed as a promising way to improve the packet processing performance.Fourthly, a novel Self-Described Buffer(SDB) management technology is introduced to eliminate the overheads of the allocation and deallocation of the packet buffers offloaded to FPGA. Then, an evaluation testbed, named PIOT(Packet I/O Testbed), is designed and implemented to evaluate the packet forwarding performance. I/O capacity of different commodity multi-core CPUs and the performance of optimization methods are assessed and compared based on PIOT. At last, the future work of packet processing optimization on multi-core CPUs is discussed.
