A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency div...A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.展开更多
To meet the demands for different supply voltage levels on SOC required by digital modules like CPU core and analog modules,a novel dual-output charge pump is proposed. The charge pump can output a step-up and a step-...To meet the demands for different supply voltage levels on SOC required by digital modules like CPU core and analog modules,a novel dual-output charge pump is proposed. The charge pump can output a step-up and a step-down voltage simultaneously with a high driving capability. The multiple gain pair technique was introduced to enhance its efficiency. The proposed co-use technology for capacitors and switch arrays reduced its cost. The charge pump was designed and fabricated in a TSMC 0.35μm mixed-signal CMOS process. A group of analytical equations were derived to model its static characteristics. A state-space model was derived to describe its small-signal dynamic behavior. Analytical predictions were verified by Spectre simulation and testing. The consistency of simulated results as well as test results with analytical predictions demonstrated the high precision of the derived analytical equations and the developed models.展开更多
An asymmetry power clock,4 phase power clock supplying the power to the DSCRL(dual swing charge recovery logic) adiabatic circuit is presented.It is much simpler than the 6 phase power clock,symmetry power clock,us...An asymmetry power clock,4 phase power clock supplying the power to the DSCRL(dual swing charge recovery logic) adiabatic circuit is presented.It is much simpler than the 6 phase power clock,symmetry power clock,used in the DSCRL adiabatic circuit.Although the 4 phase power clock is simpler,the DSCRL adiabatic circuit still shows good performance and high efficiency of energy transfer and recovery.This conclusion has been proved by the result of the HSPICE simulation using the 0 6μm CMOS technology.展开更多
Oscillator IC technique is developed by combining injecting synchronization technique with a ring VCO.Using the technique,a novel 2 488GHz of monolithical integrated injected synchronized ring VCO (ISRVCO) is realize...Oscillator IC technique is developed by combining injecting synchronization technique with a ring VCO.Using the technique,a novel 2 488GHz of monolithical integrated injected synchronized ring VCO (ISRVCO) is realized in a standard 0 25μm CMOS process.The ISRVCO is characterized by the following performances: -100dBc /Hz@1MHz at free running frequency,-91 7dBc/Hz@10kHz when injection is locked.With the 3 3V of power supply,the tuning range is 150MHz and the locking range is 100MHz with 50m V p p signal injection.展开更多
A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a...A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a clock and data recovery＇ circuit （CDR）. Each sub-model is constructed based on the architecture of a circuit. The noise and jitter in each block such as shot noise, thermal noise, deterministic and random jitter are also considered. The performance of the whole receiver can be evaluated by the simulation of the behavior model, which is faster than the ordinary circuit model and more accurate than the analytical model. The whole model is implemented with C ＋＋ and simulated in Microsoft Visual C ＋＋ 6. 0. Using the Monte Carlo method, the EPON receiver is simulated. The simulation results show a good agreement with experimental ones.展开更多
Aiming at the application of a wireless sensor network to locating miners in underground mine,we design a wireless sensor network location node system,considering the communication performance and the intrinsic safety...Aiming at the application of a wireless sensor network to locating miners in underground mine,we design a wireless sensor network location node system,considering the communication performance and the intrinsic safety. The location node system consists of a mobile node,several fixed nodes,and a sink node,all of whose circuits were designed based on CC2430. A varistor and a RC circuit were used in the reset circuit of a sensor node to guarantee the intrinsic safety by reducing discharge energy,the theoretical analysis of the discharge energy shows that the reset circuit is an intrinsic safety one. The analysis and simulation about the performance of the location node system are discussed,such as network communication delay and packet loss rate,the results show that the highest network communication delay of the system is about 0.11 seconds,and the highest packet loss rate is about 0.13,which assures the location node system has a high reliability,and can locate miners in the underground mine.展开更多
文摘A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.
文摘To meet the demands for different supply voltage levels on SOC required by digital modules like CPU core and analog modules,a novel dual-output charge pump is proposed. The charge pump can output a step-up and a step-down voltage simultaneously with a high driving capability. The multiple gain pair technique was introduced to enhance its efficiency. The proposed co-use technology for capacitors and switch arrays reduced its cost. The charge pump was designed and fabricated in a TSMC 0.35μm mixed-signal CMOS process. A group of analytical equations were derived to model its static characteristics. A state-space model was derived to describe its small-signal dynamic behavior. Analytical predictions were verified by Spectre simulation and testing. The consistency of simulated results as well as test results with analytical predictions demonstrated the high precision of the derived analytical equations and the developed models.
文摘An asymmetry power clock,4 phase power clock supplying the power to the DSCRL(dual swing charge recovery logic) adiabatic circuit is presented.It is much simpler than the 6 phase power clock,symmetry power clock,used in the DSCRL adiabatic circuit.Although the 4 phase power clock is simpler,the DSCRL adiabatic circuit still shows good performance and high efficiency of energy transfer and recovery.This conclusion has been proved by the result of the HSPICE simulation using the 0 6μm CMOS technology.
文摘Oscillator IC technique is developed by combining injecting synchronization technique with a ring VCO.Using the technique,a novel 2 488GHz of monolithical integrated injected synchronized ring VCO (ISRVCO) is realized in a standard 0 25μm CMOS process.The ISRVCO is characterized by the following performances: -100dBc /Hz@1MHz at free running frequency,-91 7dBc/Hz@10kHz when injection is locked.With the 3 3V of power supply,the tuning range is 150MHz and the locking range is 100MHz with 50m V p p signal injection.
文摘A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a clock and data recovery＇ circuit （CDR）. Each sub-model is constructed based on the architecture of a circuit. The noise and jitter in each block such as shot noise, thermal noise, deterministic and random jitter are also considered. The performance of the whole receiver can be evaluated by the simulation of the behavior model, which is faster than the ordinary circuit model and more accurate than the analytical model. The whole model is implemented with C ＋＋ and simulated in Microsoft Visual C ＋＋ 6. 0. Using the Monte Carlo method, the EPON receiver is simulated. The simulation results show a good agreement with experimental ones.
基金Projects 20070411065 supported by the China Postdoctoral Science Foundation0801028B by the Jiangsu Postdoctoral Science Research Foundation
文摘Aiming at the application of a wireless sensor network to locating miners in underground mine,we design a wireless sensor network location node system,considering the communication performance and the intrinsic safety. The location node system consists of a mobile node,several fixed nodes,and a sink node,all of whose circuits were designed based on CC2430. A varistor and a RC circuit were used in the reset circuit of a sensor node to guarantee the intrinsic safety by reducing discharge energy,the theoretical analysis of the discharge energy shows that the reset circuit is an intrinsic safety one. The analysis and simulation about the performance of the location node system are discussed,such as network communication delay and packet loss rate,the results show that the highest network communication delay of the system is about 0.11 seconds,and the highest packet loss rate is about 0.13,which assures the location node system has a high reliability,and can locate miners in the underground mine.
