基于漏磁检测的钢管探伤监控系统设计

针对钢管漏磁检测的特殊性,设计开发了一种带有干扰滤波的探伤监控系统,采用信号接收模块配合多串口卡,开辟了多个内存缓冲区,将数据进行多线程并行分析处理,极大地提高了数据处理的速度和检测的实时性。采用均值平移小波阈值去噪法对漏磁检测信号进行降噪处理,有效降低了测量噪音等干扰因素的影响,并消除伪吉布斯现象。软件部分利用Visual Studio C#进行开发,可以实现无人值守条件下的全自动流水线检测控制、自动钢管缺陷判断、报警和分析处理等功能。系统具有高的实用性和可靠性。

Design of small-area multi-bit antifuse-type 1 kbit OTP memory

A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS （complementary metal-oxide semiconductor） process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm× 327 μ,, and the read current is simulated to be 30.4 μA.

Study and application of reinforcement learning based on DAI in cooperative strategy of robot soccer

A dynamic cooperation model of multi-agent is established by combining reinforcement learning with distributed artificial intelligence(DAI),in which the concept of individual optimization loses its meaning because of the dependence of repayment on each agent itself and the choice of other agents.Utilizing the idea of DAI,the intellectual unit of each robot and the change of task and environment,each agent can make decisions independently and finish various complicated tasks by communication and reciprocation between each other.The method is superior to other reinforcement learning methods commonly used in the multi-agent system.It can improve the convergence velocity of reinforcement learning,decrease requirements of computer memory,and enhance the capability of computing and logical ratiocinating for agent.The result of a simulated robot soccer match proves that the proposed cooperative strategy is valid.

RECONFIGURABLE RDMA COMMUNICATION FRAMEWORK OF MULTI-DSP

The processing speed of the communication between nodes in a parallel processor has become the major bottleneck of the processor's performance.RDMA(Remote Direct Memory Access) technology has drawn more attention recently due to its capability of transferring a larger amount of data, higher speed and reliability.4DSP(4 Digital Signal Processing) module comprised of Tiger-SHARC201 chip is connected by LVDS(Low Voltage Differential Signal) circuits.This paper proposes a general and reconfigurable RDMA platform and its corresponding communication protocol with all the routes linked based on the zero copy.The protocol transfers message of DSP by interrupting of DMA and is applied on massive remote image impression, which reduces memory needs and working burden of CPU.The experiment results show this platform is efficient, flexible, and expandable of being integrated to a larger scale in the next development stages.

Multi-core optimization for conjugate gradient benchmark on heterogeneous processors

Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores.