采用Ga As衬底增强/耗尽型赝配高电子迁移率晶体管（E/D PHEMT）工艺研制了一款6～10 GHz多功能微波单片集成电路（MMIC）。其集成了4个单刀双掷开关、6 bit数控移相器、6 bit数控衰减器、3个放大器和14 bit并口驱动电路。测试结果表明...采用Ga As衬底增强/耗尽型赝配高电子迁移率晶体管（E/D PHEMT）工艺研制了一款6～10 GHz多功能微波单片集成电路（MMIC）。其集成了4个单刀双掷开关、6 bit数控移相器、6 bit数控衰减器、3个放大器和14 bit并口驱动电路。测试结果表明：接收支路增益大于8 d B,1 d B压缩点输出功率大于3 d Bm;发射支路增益大于1 d B,1 d B压缩点输出功率大于8 d Bm。移相64态均方根误差小于3°,衰减64态均方根误差小于1 d B。在工作频带内接收和发射两种状态下,输入输出驻波比均小于1.5∶1。经过版图优化后,芯片尺寸为3.5 mm×5.1 mm。该多功能MMIC可用于微波收发组件,对传输信号进行幅相控制。展开更多
ABC95 array computer is a multi-function network computer based on FPGA technology. A notable feature of ABC95 array computer is the support of complex interconnection, which determines that the computer must have eno...ABC95 array computer is a multi-function network computer based on FPGA technology. A notable feature of ABC95 array computer is the support of complex interconnection, which determines that the computer must have enough I/O band and flexible communications between Pes. The authors designed the interconnecting network chips of ABC95 and realized a form of multi-function interconnection. The multi-function interconnecting network supports conflict-free access from processors to memory matrix and the MESH network of enhanced processors to processor communications. The design scheme has been proved feasible by experiment.展开更多
文摘采用Ga As衬底增强/耗尽型赝配高电子迁移率晶体管（E/D PHEMT）工艺研制了一款6～10 GHz多功能微波单片集成电路（MMIC）。其集成了4个单刀双掷开关、6 bit数控移相器、6 bit数控衰减器、3个放大器和14 bit并口驱动电路。测试结果表明：接收支路增益大于8 d B,1 d B压缩点输出功率大于3 d Bm;发射支路增益大于1 d B,1 d B压缩点输出功率大于8 d Bm。移相64态均方根误差小于3°,衰减64态均方根误差小于1 d B。在工作频带内接收和发射两种状态下,输入输出驻波比均小于1.5∶1。经过版图优化后,芯片尺寸为3.5 mm×5.1 mm。该多功能MMIC可用于微波收发组件,对传输信号进行幅相控制。
文摘ABC95 array computer is a multi-function network computer based on FPGA technology. A notable feature of ABC95 array computer is the support of complex interconnection, which determines that the computer must have enough I/O band and flexible communications between Pes. The authors designed the interconnecting network chips of ABC95 and realized a form of multi-function interconnection. The multi-function interconnecting network supports conflict-free access from processors to memory matrix and the MESH network of enhanced processors to processor communications. The design scheme has been proved feasible by experiment.
