Polysilicon Over-Etching Time Control of Advanced CMOS Processing with Emission Microscopy

The emission microscopy （EMMI） test is proposed as an effective method to control the polysilicon over-etching time of advanced CMOS processing combined with a novel test structure, named a poly-edge structure. From the values of the breakdown voltage （Vbd） of MOS capacitors （poly-edge structure） ,it was observed that,with for the initial polysilicon etching-time, almost all capacitors in one wafer failed under the initial failure model. With the increase of polysilicon over-etching time, the number of the initial failure capacitors decreased. Finally, no initial failure capacitors were observed after the polysilicon over-etching time was increased by 30s. The breakdown samples with the initial failure model and intrinsic failure model underwent EMMI tests. The EMMI test results show that the initial failure of capacitors with poly-edge structures was due to the bridging effect between the silicon substrate and the polysilicon gate caused by the residual polysilicon in the ditch between the shallow-trench isolation region and the active area, which will short the polysilicon gate with silicon substrate after the silicide process.

一种改善内部高速振荡器低温良率的工艺方法

MCU芯片内部高速振荡器(HRC)的低温度敏感性对其在控制领域的应用至关重要,通过优化晶圆制造工艺来降低温度敏感性提升良率具有重要的意义。通常晶圆上有源区的图形密度差异会引起大块浅沟槽隔离区域的碟形化,在后续的多晶硅蚀刻步骤中引入有源区损伤,进而使器件的实际电性参数偏离预期值,最后使低温条件下HRC频率精度降低。本文通过在晶圆的制作工艺中,增加浅沟槽隔离化学机械研磨步骤后氮化硅剩余厚度来减少大块浅沟槽隔离区域的碟形化,同时在多晶硅光刻步骤中减少抗反射涂层厚度去改善抗反射涂层厚度的均一性,最后在多晶硅蚀刻步骤中相应的减少蚀刻时间去避免过蚀刻,进而可以有效地改善有源区损伤。通过这种工艺优化方式,低温晶圆级探针(CP)测试时HRC频率精度分布更集中并且接近目标频率,有效提升了在低温条件下HRC的频率精度,晶圆边缘HRC良率提升可以达到1%。