数字上变频(DUC)是射频拉远单元(RRU)的核心部件之一。研究了基于FPGA的数字上变频算法,依据WCDMA相关协议设计了DUC系统。系统的内插器采用多项滤波结构,并应用泰勒校正算法提高数控振荡器(NCO)的杂散抑制比。用VerilogHDL进行逻辑实...数字上变频(DUC)是射频拉远单元(RRU)的核心部件之一。研究了基于FPGA的数字上变频算法,依据WCDMA相关协议设计了DUC系统。系统的内插器采用多项滤波结构,并应用泰勒校正算法提高数控振荡器(NCO)的杂散抑制比。用VerilogHDL进行逻辑实现、仿真和验证,并在FPGA上综合实现。由ADS软件生成的WCDMA基带数据经上变频后在Vector Signal Analyzer软件中进行数据解调,以测试系统的性能。展开更多
A 1.1 - 1.2GHz CMOS high phase accuracy,low amplitude mismatch quadrature LO driver is presented,which consists of a high frequency amplifier,an integrated poly phase filter, and an I/Q phase and magnitude calibration...A 1.1 - 1.2GHz CMOS high phase accuracy,low amplitude mismatch quadrature LO driver is presented,which consists of a high frequency amplifier,an integrated poly phase filter, and an I/Q phase and magnitude calibration circuit（PMCC）. The proposed PMCC uses a feed-forward calibration technique. It improves the phase accuracy and reduces the amplitude mismatch with low power consumption. Simulation results show that phase error with PMCC is reduced to about one half and the amplitude mismatch is reduced to about one tenth, when compared to the LO driver without PMCC. Moreover,the calibration circuit also functions as a buffer to drive mixers, thus no additional buffer is needed in this design. The LO driver is implemented in a TSMC 0.25μm CMOS process. Experimental results show that the LO driver achieves high quadrature accuracy （〈2°） and low amplitude mismatch （0. 1%）. It has about 5.25dB gain and dissipates 6mA from the 2.5V power supply. The size of the die area is only 1.0mm×1.0mm.展开更多
文摘数字上变频(DUC)是射频拉远单元(RRU)的核心部件之一。研究了基于FPGA的数字上变频算法,依据WCDMA相关协议设计了DUC系统。系统的内插器采用多项滤波结构,并应用泰勒校正算法提高数控振荡器(NCO)的杂散抑制比。用VerilogHDL进行逻辑实现、仿真和验证,并在FPGA上综合实现。由ADS软件生成的WCDMA基带数据经上变频后在Vector Signal Analyzer软件中进行数据解调,以测试系统的性能。
文摘A 1.1 - 1.2GHz CMOS high phase accuracy,low amplitude mismatch quadrature LO driver is presented,which consists of a high frequency amplifier,an integrated poly phase filter, and an I/Q phase and magnitude calibration circuit（PMCC）. The proposed PMCC uses a feed-forward calibration technique. It improves the phase accuracy and reduces the amplitude mismatch with low power consumption. Simulation results show that phase error with PMCC is reduced to about one half and the amplitude mismatch is reduced to about one tenth, when compared to the LO driver without PMCC. Moreover,the calibration circuit also functions as a buffer to drive mixers, thus no additional buffer is needed in this design. The LO driver is implemented in a TSMC 0.25μm CMOS process. Experimental results show that the LO driver achieves high quadrature accuracy （〈2°） and low amplitude mismatch （0. 1%）. It has about 5.25dB gain and dissipates 6mA from the 2.5V power supply. The size of the die area is only 1.0mm×1.0mm.
