A 12 Gbit/s limiting amplifier for fiber-optic transmission system is realized in a 2μm GaAs HBT technology. The whole circuit consists of an input buffer, three similar amplifier cells, an output buffer for driving ...A 12 Gbit/s limiting amplifier for fiber-optic transmission system is realized in a 2μm GaAs HBT technology. The whole circuit consists of an input buffer, three similar amplifier cells, an output buffer for driving 50 ft transmission lines and a pair of feedback networks for offset cancellation. At a positive supply voltage of 2 V and a negative supply voltage of - 2V, the power dissipation is about 280 mW. The small-signal gain is higher than 46 dB and the input dynamic range is about 40 dB with a constant single-ended output voltage swing of 400 mV. Satisfactory eye-diagrams are obtained at the bit rate of 12 Gbit/s limited by the test set-up. The chip area is 1.15 mm ×0.7 mm.展开更多
A novel programmable gain amplifier（ PGA） based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers（ VGA）,a binary-weighted switching technique is employed...A novel programmable gain amplifier（ PGA） based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers（ VGA）,a binary-weighted switching technique is employed to vary the current-steering transistors＇ aspect ratio to change their transconductance, and hence, an accurate gain step size of 6dB is achieved. The constant-g_m biasing technique and the matching of the transistors and resistors ensures that the gain of the proposed topology is independent of the variation of process, voltage and temperature（ PVT）. P-well NMOS（ Nmetal oxide semiconductor） transistors are utilized to eliminate the influence of back-gate effect which will induce gain error.The source-degeneration technique ensures good linearity performance at a low gain. The proposed PGA is fabricated in a0.18 μm CMOS（ complementary metal oxide semiconductor）process. The measurement results show a variable gain ranging from 0 to24 dB with a step size of 6 dB and a maximum gain error of 0. 3dB. A constant 3dB bandwidth of 210 MHz is achieved at different gain settings. The measured output 3rd intercept point（OIP3） and minimum noise figure（ NF） are20. 9 dBm and 11.1 dB, respectively. The whole PGA has a compact layout of 0.068 mm^2. The total power consumption is4. 8 mW under a 1. 8 V supply voltage.展开更多
A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz' s 0.35μmSiGe BiCMOS process.It was fully integrated excluding the inductors and the output matching network.Under a single 3.3V...A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz' s 0.35μmSiGe BiCMOS process.It was fully integrated excluding the inductors and the output matching network.Under a single 3.3V supply voltage,the off-chip bonding test results indicated that the circuit has a smallsignal gain of more than 24dB,the input and output reflectance are less than- 24dB and-10dB,re-spectively,and the maximal output power is 23.5 dBm.At output power of 23.1 dBm,the PAE(poweradded efficiency)is 30.2%,the IMD2 and IMD3 are less than- 32 dBc and-46 dBc,respectively.The chip size is 1.27mm ×0.9mm.展开更多
A 130 nm CMOS complementary-conducting-strip transmission line(CCS-TL)based multi-stage amplifier beyond 100 GHz was presented in this paper. Different structural parameters were investigated to achieve higher quality...A 130 nm CMOS complementary-conducting-strip transmission line(CCS-TL)based multi-stage amplifier beyond 100 GHz was presented in this paper. Different structural parameters were investigated to achieve higher quality factor for the matching circuits. Moreover, CCS-TL based Marchand balun was implemented to achieve higher output power. The measured small signal gain was higher than 5 d B from 101 GHz to 110 GHz. DC power consumption was 67.2 mW with V_D=1.2 V, and the chip size including contact PADs was 1.12 mm×0.81 mm.展开更多
文摘A 12 Gbit/s limiting amplifier for fiber-optic transmission system is realized in a 2μm GaAs HBT technology. The whole circuit consists of an input buffer, three similar amplifier cells, an output buffer for driving 50 ft transmission lines and a pair of feedback networks for offset cancellation. At a positive supply voltage of 2 V and a negative supply voltage of - 2V, the power dissipation is about 280 mW. The small-signal gain is higher than 46 dB and the input dynamic range is about 40 dB with a constant single-ended output voltage swing of 400 mV. Satisfactory eye-diagrams are obtained at the bit rate of 12 Gbit/s limited by the test set-up. The chip area is 1.15 mm ×0.7 mm.
基金The National Natural Science Foundation of China(No.61306069)
文摘A novel programmable gain amplifier（ PGA） based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers（ VGA）,a binary-weighted switching technique is employed to vary the current-steering transistors＇ aspect ratio to change their transconductance, and hence, an accurate gain step size of 6dB is achieved. The constant-g_m biasing technique and the matching of the transistors and resistors ensures that the gain of the proposed topology is independent of the variation of process, voltage and temperature（ PVT）. P-well NMOS（ Nmetal oxide semiconductor） transistors are utilized to eliminate the influence of back-gate effect which will induce gain error.The source-degeneration technique ensures good linearity performance at a low gain. The proposed PGA is fabricated in a0.18 μm CMOS（ complementary metal oxide semiconductor）process. The measurement results show a variable gain ranging from 0 to24 dB with a step size of 6 dB and a maximum gain error of 0. 3dB. A constant 3dB bandwidth of 210 MHz is achieved at different gain settings. The measured output 3rd intercept point（OIP3） and minimum noise figure（ NF） are20. 9 dBm and 11.1 dB, respectively. The whole PGA has a compact layout of 0.068 mm^2. The total power consumption is4. 8 mW under a 1. 8 V supply voltage.
基金Supported by the High Technology Research and Development Programme of China (2006AA03Z418)
文摘A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz' s 0.35μmSiGe BiCMOS process.It was fully integrated excluding the inductors and the output matching network.Under a single 3.3V supply voltage,the off-chip bonding test results indicated that the circuit has a smallsignal gain of more than 24dB,the input and output reflectance are less than- 24dB and-10dB,re-spectively,and the maximal output power is 23.5 dBm.At output power of 23.1 dBm,the PAE(poweradded efficiency)is 30.2%,the IMD2 and IMD3 are less than- 32 dBc and-46 dBc,respectively.The chip size is 1.27mm ×0.9mm.
基金Supported by the National High Technology Research and Development Program of China(“863”ProgramNo.2015AA01A703)
文摘A 130 nm CMOS complementary-conducting-strip transmission line(CCS-TL)based multi-stage amplifier beyond 100 GHz was presented in this paper. Different structural parameters were investigated to achieve higher quality factor for the matching circuits. Moreover, CCS-TL based Marchand balun was implemented to achieve higher output power. The measured small signal gain was higher than 5 d B from 101 GHz to 110 GHz. DC power consumption was 67.2 mW with V_D=1.2 V, and the chip size including contact PADs was 1.12 mm×0.81 mm.
