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快速跳频大数合并和软判决线性合并抗部分频带干扰性能分析和仿真
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作者 黄东平 张申如 《信息通信》 2008年第6期20-23,共4页
本文分析了快速跳频在部分频带干扰和高斯白噪声信道下的系统误码性能,推导了接收机采用了大数合并的误码率表达式,采用特征函数的办法重新分析了软判决线性合并时的误码率表达式。仿真结果表明,两种合并方法随着分集数的增大误码性能... 本文分析了快速跳频在部分频带干扰和高斯白噪声信道下的系统误码性能,推导了接收机采用了大数合并的误码率表达式,采用特征函数的办法重新分析了软判决线性合并时的误码率表达式。仿真结果表明,两种合并方法随着分集数的增大误码性能都下降,都不能抗全频带干扰。在干扰比较小时,软判决线性合并整体性能要好于大数合并。 展开更多
关键词 快速跳频 软判决 线性合并 大数合并
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An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC 被引量:6
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作者 LI Weitao LI Fule +2 位作者 YANG Changyi LI Shengjing WANG Zhihua 《China Communications》 SCIE CSCD 2015年第5期14-21,共8页
A low-power 14-bit 150MS/s an- alog-to-digital converter (ADC) is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor shari... A low-power 14-bit 150MS/s an- alog-to-digital converter (ADC) is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier (SHA) is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer. 展开更多
关键词 analog-to-digital conversion LOWPOWER CALIBRATION high speed and high reso-lution pipelined analog-to-digital converter CMOS analog integrated circuits
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