基于SST39VF640x闪存的擦写器设计

为了实现对SST39VF640x闪存4M空间的字编程,需要搭建一个16位的数据通道,使得C51微处理器每次对外存的访问,都能以双字节的方式进行,同时,须补齐系统指令寻址能力的短板,以满足对4M地址的I/O操作需求。实施中,充分利用C51外总线固有时序,并引入一定数量的寄存器,预设或锁存地址和数据,在读/写周期内,借助/RD、/WR和ALE的协调,完成总线信息的归并及拆分。通过总线接口的再构造,使本质上属于字节操作的微系统具有了字传输能力,并对擦/写流程进行简化,提出了具体实施方案,大幅缩短了试验周期,加快了试验进程。

10 Gbit/s PRBS tester implemented in FPGA

The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.

一种高速可编程字图形产生方法

介绍了高速误码测试仪中,产生较长可编程字图形的一种方法。并给出了实验结果。其最长字长可达2048比特。速率在1～700MHz之间。

Framework of Digital Machining Process Planning Platform for Cylinder Body Part

Digital factory technology is an advanced manufacturing technology served as to establish a bridge between the process of product development and manufacturing.In terms of application for digital factory technology in machining,especially in machining of a complicated part such as a cylinder body part,a concept of digital process planning and its framework are proposed.Its components including machining domain knowledge model,machining knowledge base,machining resource base and process planning system are studied.A machining knowledge model in tree form and an object-driven knowledge reasoning mechanism are used for machining knowledge base.The process planning system is a user interface that leads a planner to finish the planning process.A case about a cylinder head part is given to demonstrate how the platform works.The framework of digital process planning is the foundation of some intelligent CAPP systems and helps to production line planning.

THE DESIGN OF VMEBUS BRIDGE CONTROLLER WITH SHARC BUS

Targeting at the high expense and inflexibility to realize VMEbus bridge controller by professional Integrated Circuit (IC), this paper presents a scheme of adopting CPLD/FPGA (Complicated Programmable Logic Device/Field Programmable Gate Array) to design bridge controller between VMEbus and local bus. SHARC DSP (Digital Signal Processor) bus is an example. It has functions of nearly entire master/slave interface of VMEbus, and can act as DMA (Direct Memory Access) controller and perform block transfer in DMA or master processor initiative way without length limit. External circuit of the design is very simple. In comparison with special ICs, it has high performance to price ratio and can be easily applied to local buses of other processors with quite a little modification.

Design of Roof Cover Structures by Help of Numerical Models Defined in Formian

Numerical models defined by means of a suitably assumed set of parameters make it possible to select the optimal structural solution for the given or assumed conditions. The paper presents examples of applications of numerical models defined in the programming language Formian during the shaping processes of various types of spatial structural systems designed for roof covers. These types of numerical models can be relatively easily adapted to the requirements, which can be frequently changed during the investment process, what makes possible a considerable reducing of costs and time of design of the space structures having even the very complex shapes. The advantageous features of application of numerical models defined in Formian are presented in models determined for selected forms of the roof covers designed also by means of a simple type of a space frame. In the paper, there are some presented visualizations made on bases of these models defining mainly for structural systems developed recently by the author for certain types of the dome covers. The proposed structural systems are built by means of the successive spatial hoops or they are created as unique forms of the geodesic dome structures.

A force feedback master finger in exoskeleton type

In order to eliminate the drawbacks of conventional force feedback gloves, a new type of master fin- ger has been developed. By utilizing three ＂four-bar mechanism joint＂ in series and wire coupling mecha- nism, the master finger transmission ratio is kept exactly 1：1.4：1 in the whole movement range and it can make active motions in both extension and flexion directions. Additionally, to assure faster data transmission and near zero delay in the master-slave operation, a digital signal processing/field programmable gate array （DSP/FPGA-FPGA） structure with 200μs cycle time is designed. The operating modes of the master finger can be contact or non-contact, which depends on the motion states of a slave finger, free motion or constrained motion. The position control employed in non-contact mode ensures unconstrained motion and the force control adopted in contact mode guarantees natural contact sensation. To evaluate the performances of the master finger, an experiment between the master finger and a DLR/HTT dexterous finger is conducted. The results demonstrate that this new type master finger can augment telepresence.

Performance Analysis of PMSM Equations Computation

The paper deals with the comparison of three different digital devices used for the computing of permanent magnet synchronous motor （PMSM） model. Model is used for virtual high frequency injection method （VHFIM） sensorless control, where injection and acting voltages are virtual ones. For computing the whole PMSM model, differential equations are used. The paper is focused on performance analysis of computing speed and accuracy of field-programmable gate array （FPGA） device, digital signal controller and Power PC microcontroller and results are compared.

Transposable elements at the center of the crossroads between embryogenesis, embryonic stem cells, reprogramming,and long non-coding RNAs

Transposable elements(TEs) are mobile genomic sequences of DNA capable of autonomous and nonautonomous duplication. TEs have been highly successful,and nearly half of the human genome now consists of various families of TEs. Originally thought to be non-functional,these elements have been co-opted by animal genomes to perform a variety of physiological functions ranging from TE-derived proteins acting directly in normal biological functions, to innovations in transcription factor logic and influence on epigenetic control of gene expression. During embryonic development, when the genome is epigenetically reprogrammed and DNA-demethylated, TEs are released from repression and show embryonic stage-specific expression, and in human and mouse embryos, intact TEderived endogenous viral particles can even be detected. Asimilar process occurs during the reprogramming of somatic cells to pluripotent cells: When the somatic DNA is demethylated, TEs are released from repression. In embryonic stem cells(ESCs), where DNA is hypomethylated, an elaborate system of epigenetic control is employed to suppress TEs, a system that often overlaps with normal epigenetic control of ESC gene expression. Finally, many long non-coding RNAs(lnc RNAs) involved in normal ESC function and those assisting or impairing reprogramming contain multiple TEs in their RNA. These TEs may act as regulatory units to recruit RNA-binding proteins and epigenetic modifiers. This review covers how TEs are interlinked with the epigenetic machinery and lnc RNAs, and how these links influence each other to modulate aspects of ESCs,embryogenesis, and somatic cell reprogramming.

A digital energy spectroscopy based on FIR filter

We designed a universal digital energy spectroscopy based on online digital signal processing. A prototype system was built and tested. Signals from radiation detectors were processed via a digital filter whose coefficients could be modified without changing the hardware. The paper introduces the hardware design of the digital energy spectroscopy system as well as the full set of software consisting of the selection of the coefficients of the finite impulse response (FIR) filter and the coding in the field-programmable gate array (FPGA). The system was tested with the high purity germanium (HPGe) detector. The results showed that this prototype can achieve an energy resolution close to that of a traditional multi-channel analyzer (MCA) with a much higher counting rate.

A fast digital timing and analysis system based on real-time dCFD technique for nuclear physics experiments

In this paper a fast digital real-time spectrometer was developed for timing and analysis of nuclear pulse signals. The hardware system design and algorithm implementation with field-programming gate array （FPGA） and digital signal processor （DSP） were introduced. The performance of the digital constant fraction discrimination （dCFD） platform was experimentally tested with Agilent 80 MHz function/arbitrary waveform generator and LaC13：Ce3＋ scintillator detector for 22Na positron annihilation gamma spectroscopy. The amplitude and time information of ＂/photon was online obtained. The energy resolution could be 5.525% and the timing resolution 293.75 ps, the system error estimation of dCFD approach was also studied. The results showed that this spectrometer achieved a timing resolution close to that of traditional CFD timing resolution with a more sim- plified system structure.

High-resolution data acquisition technique in broadband seismic observation systems

The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10–20 d B lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter(ADC) chips with more than 24 bits in the market. In this paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus facilitating higher resolution and larger dynamic range seismic data acquisition. Experimental results show that, within the 0.1–40 Hz frequency range, the circuit board's dynamic range reaches 158.2 d B, its resolution reaches 25.99 bits, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even completely resolve the amplitude-limitation problem that so commonly occurs with broadband observation instruments during strong earthquakes.