A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works...A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.展开更多
In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for...In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.展开更多
This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challen...This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.展开更多
Vector tracking changes the classical structure of receivers. Combining signal tracking and navigation solution,vector tracking can realize powerful processing capabilities by the fusion technique of receiving channel...Vector tracking changes the classical structure of receivers. Combining signal tracking and navigation solution,vector tracking can realize powerful processing capabilities by the fusion technique of receiving channel and feedback correction. In this paper,we try to break through the complicated details of numerical analysis,consider the overall influencing factors of the residual in observed data,and use the intrinsic link between a conventional receiver and a vector receiver. A simple method for performance analysis of the vector tracking algorithm is proposed. Kalman filter has the same steady performance with the classic digital lock loop through the analysis of the relation between gain and band width. The theoretical analysis by the least squares model shows that the reduction of range error is the basis for the superior performance realized by vector tracking. Thus,the bounds of its performance enhancement under weak signal and highly dynamic conditions can be deduced. Simulation results verify the effectiveness of the analysis presented here.展开更多
A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage change...A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.展开更多
A method of implementing high cost-effective and highly integrated digital lock-in amplifier with microcontroller is discussed. And the digital lock-in amplifier is more suitable for meastwing lowfrequency weak signal...A method of implementing high cost-effective and highly integrated digital lock-in amplifier with microcontroller is discussed. And the digital lock-in amplifier is more suitable for meastwing lowfrequency weak signal. Digital signal sequence is obtained through sampling signal measured over an integer number of signal periods, but digital reference sequence is acquired through mathematical operation, then digital phase sensitive detection can be implemented by calculating the cross-correlation function of digital signal sequence and digital reference sequence. In addition, the frequency response and phase character of the digital lock-in amplifier is analyzed. Finally, the designed digital lock-in amplifier is achieved. Expermental results show that the digital lock-in amplifier can be used for measuring weak signal with low ignal-to-noise ratio.展开更多
Introducing a System-on-Chip （SoC） microcontroller （C8051F350） into a ceramic pressure sensor has resulted in the design of a intelligent sensor. An improved algorithm for digital phassensitive detection is used ...Introducing a System-on-Chip （SoC） microcontroller （C8051F350） into a ceramic pressure sensor has resulted in the design of a intelligent sensor. An improved algorithm for digital phassensitive detection is used to perform lock-in amplification of the sensor signal. The compensation for the sensor error is realized by the detection of the sensor＇s supply voltage and working temperature. The system also has the function of short/open circuit fault detection and can ommamicate with other digital equipment through an RS-485 communication interface. In the design, full utilization of the SoC microcontroller＇ s internal resource results in the simple hardware structure. Experimental results show that the error of the sensor is less than 0.5% at range ratio 1 ： 10. Employing the microcontroller and using lock-in amplification algorithm are an effective method for achieving an intelligent sensor of slowly-varying physical quantities, thereby improving the measuring accuracy and performance.展开更多
文摘A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.
基金The National Natural Science Foundation of China(No. 60974116 )the Research Fund of Aeronautics Science (No.20090869007)Specialized Research Fund for the Doctoral Program of Higher Education (No. 200902861063)
文摘In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.
文摘This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.
基金Supported by the National Natural Science Foundation of China(No.41474027)the National Defense Basic Science Project(JCKY2016110B004)
文摘Vector tracking changes the classical structure of receivers. Combining signal tracking and navigation solution,vector tracking can realize powerful processing capabilities by the fusion technique of receiving channel and feedback correction. In this paper,we try to break through the complicated details of numerical analysis,consider the overall influencing factors of the residual in observed data,and use the intrinsic link between a conventional receiver and a vector receiver. A simple method for performance analysis of the vector tracking algorithm is proposed. Kalman filter has the same steady performance with the classic digital lock loop through the analysis of the relation between gain and band width. The theoretical analysis by the least squares model shows that the reduction of range error is the basis for the superior performance realized by vector tracking. Thus,the bounds of its performance enhancement under weak signal and highly dynamic conditions can be deduced. Simulation results verify the effectiveness of the analysis presented here.
文摘A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.
文摘A method of implementing high cost-effective and highly integrated digital lock-in amplifier with microcontroller is discussed. And the digital lock-in amplifier is more suitable for meastwing lowfrequency weak signal. Digital signal sequence is obtained through sampling signal measured over an integer number of signal periods, but digital reference sequence is acquired through mathematical operation, then digital phase sensitive detection can be implemented by calculating the cross-correlation function of digital signal sequence and digital reference sequence. In addition, the frequency response and phase character of the digital lock-in amplifier is analyzed. Finally, the designed digital lock-in amplifier is achieved. Expermental results show that the digital lock-in amplifier can be used for measuring weak signal with low ignal-to-noise ratio.
基金supported by Research Project of "SUSTSpring Bud"(No.2008BWZ042)from Shandong University of Science and Technology
文摘Introducing a System-on-Chip （SoC） microcontroller （C8051F350） into a ceramic pressure sensor has resulted in the design of a intelligent sensor. An improved algorithm for digital phassensitive detection is used to perform lock-in amplification of the sensor signal. The compensation for the sensor error is realized by the detection of the sensor＇s supply voltage and working temperature. The system also has the function of short/open circuit fault detection and can ommamicate with other digital equipment through an RS-485 communication interface. In the design, full utilization of the SoC microcontroller＇ s internal resource results in the simple hardware structure. Experimental results show that the error of the sensor is less than 0.5% at range ratio 1 ： 10. Employing the microcontroller and using lock-in amplification algorithm are an effective method for achieving an intelligent sensor of slowly-varying physical quantities, thereby improving the measuring accuracy and performance.
