An Ultra-Low-Power Embedded EEPROM for Passive RFID Tags

An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.

Design and implementation of a new special storage server

To improve I/O speed and system performance of network storage devices, a special storage server that is an iSCSI-based network-attached storage server (iSCSI-based network-attached storage server, for short iNAS) is designed. The iNAS can provide both the file I/O and the block I/O services by an iSCSI module, and it converges with the NAS and the SAN (storage area network). The iNAS improves the I/O speed by the direct data access (zero copy) between the RAID (redundant array of inexpensive disks) controller and the user-level memory. The iNAS integrates the multi-RAID for a single storage pool by a multi-stage stripping device driver, and it implements the storage virtualization. In the experiments, the iNAS has ultra-high-throughput for both the file I/O requests and the block I/O requests.

SCDI Flash Memory Device Ⅱ:Experiments and Characteristics

Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed of SCDI device is 42μs.Under the condition of V g=-8V, V s=8V,the erasing speed is 24ms.Compared with the same size of conventional flash memory device whose corresponding parameters are 500μs and 24ms,respectively,the performance of SCDI device is remarkably improved.During manufacturing of SCDI device,the key technologies are to make the shallow step with appropriate depth and angle,along with eliminating the etch damage during the process of Si 3N 4 spacer.

找出硬盘中的坏道

对硬盘来说，最危险的就是坏道了，尤其是二手硬盘更是如此。那么我们有什么好方法来检测硬盘中的坏道呢?

An Improved Charge Pumping Method to Study Distribution of Trapped Charges in SONOS Memory

In silicon-oxide-nitride-oxide-silicon （SONOS） memory and other charge trapping memories, the charge distribution after programming operation has great impact on the devic＇s characteristics,such as reading,programming/erasing, and reliability. The lateral distribution of injected charges can be measured precisely using the charge pumping method. To improve the precision of the actual measurement, a combination of a constant low voltage method and a constant high voltage method is introduced during the charge pumping testing of the drain side and the source side, respectively. Finally, the electron distribution after channel hot electron programming in SONOS memory is obtained,which is close to the drain side with a width of about 50nm.

A Low-Power,Single-Poly,Non-Volatile Memory for Passive RFID Tags

Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.

An LFSR-based address generator using optimized address partition for low power memory BIST

Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.

Design of 32 kbit one-time programmable memory for microcontroller units

A 32 kbit OTP(one-time programmable)memory for MCUs(micro-controller units)used in remote controllers was designed.This OTP memory is used for program and data storage.It is required to apply 5.5V to BL(bit-line)and 11V to WL(word-line)for a OTP cell of 0.35μm ETOX(EEPROM tunnel oxide)type by MagnaChip.We use 5V transistors on column data paths to reduce the area of column data paths since they require small areas.In addition,we secure device reliability by using HV(high-voltage)transistors in the WL driver.Furthermore,we change from a static logic to a dynamic logic used for the WL driver in the core circuit.Also,we optimize the WD(write data)switch circuit.Thus,we can implement them with a small-area design.In addition,we implement the address predecoder with a small-area logic circuit.The area of the designed 32 kbit OTP with 5V and HV devices is 674.725μm×258.75μm(=0.1745mm2)and is 56.3% smaller than that using 3.3V devices.

DESIGN AND IMPLEMENTATION OF SINGLE-BUFFERED ROUTERS

A Single-Buffered （SB） router is a router where only one stage of shared buffering is sandwiched between two interconnects in comparison of a Combined Input and Output Queued （CIOQ） router where a central switch fabric is sandwiched between two stages of buffering. The notion of SB routers was firstly proposed by the High-Performance Networking Group （HPNG） of Stanford University, along with two promising designs of SB routers： one of which was Parallel Shared Memory （PSM） router and the other was Distributed Shared Memory （DSM） router. Admittedly, the work of HPNG deserved full credit, but all results presented by them appeared to relay on a Centralized Memory Management Algorithm （CMMA） which was essentially impractical because of the high processing and communication complexity. This paper attempts to make a scalable high-speed SB router completely practical by introducing a fully distributed architecture for managing the shared memory of SB routers. The resulting SB router is called as a Virtual Output and Input Queued （VOIQ） router. Furthermore, the scheme of VOIQ routers can not only eliminate the need for the CMMA scheduler, thus allowing a fully distributed implementation with low processing and commu- nication complexity, but also provide QoS guarantees and efficiently support variable-length packets in this paper. In particular, the results of performance testing and the hardware implementation of our VOIQ-based router （NDSC~ SR1880-TTM series） are illustrated at the end of this paper. The proposal of this paper is the first distributed scheme of how to design and implement SB routers publicized till now.

Development of OPTO-LDR coupled timer based voltage to frequency converter

This paper describes the development of a timer based voltage to frequency converter(V FC).Timer LM555is used in astable multivibrator mode with two OPTO-LDRs(light dependent resistors)in the circuitry.The frequency of timer output waveform which is measured using a digital storage oscillator(DSO)is almost linearly proportional to the applied input voltage.Hence we obtain a linear relationship between the frequency of timer output waveform and the input voltage.Because of its quasi-digital output,the main advantages of this developed converter are linear input-output relationship,small size,easy portabilityand high cost performance.In addition,the timer output waveform can be directly interfaced with personal computer or microprocessor/microcontroller for further processing of the input voltage signal without intervening any analog-to-digital converter(ADC).

Performance modeling of positive degraded task-pair with helper-thread in CMP

Helper-thread of a task can hide the memory access time of irregular data on the chip muhi-core processor （CMP）. For constructing a compiler that effectively supports the helper-thread of a task in the multi-core scenario based on the last level shared cache, this paper studies its performance stable condi- tions. Unfortunately, there is no existing model that allows extensive investigation of the impact of stable conditions, we present the base of pre-computation that is formalized by our degraded task-pair 〈 T, T＇ 〉 with the helper-thread, and its stable conditions are analyzed. Finally, a novel performance model and a constructing method of pre-computation based on our positive degraded task-pair are proposed. The efficient results are shown by our experiments. If we further exploit memory level parallelism （MLP） for our task-pair, the task-pair 〈 T, T＇ 〉 can reach better performance.

Design of small-area and high-efficiency DC-DC converter for 1 T SRAM

The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.

Development of Ferroelectric RAM （FRAM） for Mass Production

we have developed ferroelectric capacitor fabrication technique to realize low-voltage and high-density ferroelectric random access memory （FRAM）. High temperature deposited IrOxtop electrode reveals high crystalline quality which drastically reduces the degradation of ferroelectric film by preventing hydrogen diffusion into ferroelectric film. This improvement enables us to commercialize highly-reliable 1T 1C FRAM with memory density of 4 Mb or larger.

Recent development of studies on the mechanism of resistive memories in several metal oxides

Resistive switching random access memories(RRAM)have been considered to be promising for future information technology with applications for non-volatile memory,logic circuits and neuromorphic computing.Key performances of those resistive devices are approaching the realistic levels for production.In this paper,we review the progress of valence change type memories,including relevant work reported by our group.Both electrode engineering and in-situ transmission electron microscopy(TEM)high-resolution observation have been implemented to reveal the influence of migration of oxygen anions/vacancies on the resistive switching effect.The understanding of resistive memory mechanism is significantly important for device applications.

Resistive-switching tunability with size-dependent all-inorganic zero-dimensional tetrahedrite quantum dots

All-inorganic zero-dimensional(0D)tetrahedrite(Cu12Sb4S13,CAS)quantum dots(QDs)have attracted extensive attention due to their excellent optical properties,bandgap tunability,and carrier mobility.In this paper,various sized CAS QDs(5.1,6.7,and 7.9 nm)are applied as a switching layer with the structure F:Sn O2(FTO)/CAS QDs/Au,and in doing so,the nonvolatile resistive-switching behavior of electronics based on CAS QDs is reported.The SET/RESET voltage tunability with size dependency is observed for memory devices based on CAS QDs for the first time.Results suggest that differently sized CAS QDs result in different band structures and the regulation of the SET/RESET voltage occurs simply and effectively due to the uniform size of the CAS QDs.Moreover,the presented memory devices have reliable bipolar resistive-switching properties,a resistance(ON/OFF)ratio larger than 104,high reproducibility,and good data retention ability.After 1.4×10^6s of stability testing and 104cycles of quick read tests,the change rate of the ON/OFF ratio is smaller than 0.1%.Furthermore,resistiveswitching stability can be improved by ensuring a uniform particle size for the CAS QDs.The theoretical calculations suggest that the space-charge-limited currents(SCLCs),which are functioned by Cu 3d,Cu 3p and S 3p to act as electron selftrapping centers due to their quantum confinement and form conduction pathways under an electric field,are responsible for the resistive-switching effect.This paper demonstrates that CAS QDs are promising as a novel resistive-switching material in memory devices and can be used to facilitate the application of next-generation nonvolatile memory.

New design of sense amplifier for EEPROM memory

We present a new sense amplifier circuit for EEPROM memory. The topology of the sense amplifier uses a voltage sensing method,having low cost and low power consumption as well as high reliability. The sense amplifier was implemented in an EEPROM realized with an SMIC 0.35-μm 2P3M CMOS embedded EEPROM process. Under the condition that the power supply is 3.3 V,simulation results showed that the charge time is 35 ns in the proposed sense amplifier,and that the maximum average current consumption during the read period is 40 μA. The novel topology allows the circuit to function with power supplies as low as 1.4 V. The sense amplifier has been implemented in 2-kb EEPROM memory for RFID tag IC applications,and has a silicon area of only 240 μm2.

Realization of a non-markov chain in a single 2D mineral RRAM

The non-Markov process exists widely in thermodymanic process,while it usually requires the packing of many transistors and memories with great system complexity in a traditional device structure to minic such functions.Two-dimensional(2D)material-based resistive random access memory(RRAM)devices have the potential for next-generation computing systems with much-reduced complexity.Here,we achieve a non-Markov chain in an individual RRAM device based on 2D mineral material mica with a vertical metal/mica/metal structure.We find that the potassium ions(K+)in 2D mica gradually move in the direction of the applied electric field,making the initially insulating mica conductive.The accumulation of K+is changed by an electric field,and the 2D-mica RRAM has both single and double memory windows,a high on/off ratio,decent stability,and repeatability.This is the first time a non-Markov chain process has been established in a single RRAM,in which the movement of K+is dependent on the stimulated voltage as well as their past states.This work not only uncovers an intrinsic inner ionic conductivity of 2D mica,but also opens the door for the production of such RRAM devices with numerous functions and applications.