A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel acce...A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...展开更多
Recently,Content-Centric Networking(CCN) has been paid more and more attention.The modeling of CCN as an important research point is the foundation of the architecture.The past work of cache network modeling always as...Recently,Content-Centric Networking(CCN) has been paid more and more attention.The modeling of CCN as an important research point is the foundation of the architecture.The past work of cache network modeling always assumes the virtual round trip time(VRTT) is zero for simplicity.However,this assumption isn't practical and results in model error especially in CCN.CCN's router can aggregate the content requests during the VRTT to avoid content delivery repeatedly.Thus,to modeling CCN data transfer,as well as understanding how it should be managed,the VRTT shouldn't be ignored.In this paper,we model the data transfer in CCN,and propose a multi-cache with aggregation approximation(MCAA)algorithm to get the content miss rate and VRTT at each router.Simulation results show the validity of our MCAA algorithm.展开更多
This paper explains intra prediction method for High Efficiency Video Coding(HEVC).Intra prediction removes correlation of adjacent samples in spatial domain.Intra predictor requires reference images which are stored ...This paper explains intra prediction method for High Efficiency Video Coding(HEVC).Intra prediction removes correlation of adjacent samples in spatial domain.Intra predictor requires reference images which are stored in external memory.Memory access is required frequently in process of intra prediction.The proposed architecture can reduce external memory access by optimized internal buffer.展开更多
文摘A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...
基金supported by the National Basic Research Program(973) of China(No. 2012CB315801)the National Natural Science Fund(No.61302089)the fundamental research funds for the Central Universities(No. 2013RC0113)
文摘Recently,Content-Centric Networking(CCN) has been paid more and more attention.The modeling of CCN as an important research point is the foundation of the architecture.The past work of cache network modeling always assumes the virtual round trip time(VRTT) is zero for simplicity.However,this assumption isn't practical and results in model error especially in CCN.CCN's router can aggregate the content requests during the VRTT to avoid content delivery repeatedly.Thus,to modeling CCN data transfer,as well as understanding how it should be managed,the VRTT shouldn't be ignored.In this paper,we model the data transfer in CCN,and propose a multi-cache with aggregation approximation(MCAA)algorithm to get the content miss rate and VRTT at each router.Simulation results show the validity of our MCAA algorithm.
基金supported by the MKE(The Ministry of Knowledge Economy),Korea,under the ITRC(Infor mation Technology Research Center)support program supervised by the NIPA(National IT Industry Promotion Agency)(NIPA-2011-C1090-1021-0010)
文摘This paper explains intra prediction method for High Efficiency Video Coding(HEVC).Intra prediction removes correlation of adjacent samples in spatial domain.Intra predictor requires reference images which are stored in external memory.Memory access is required frequently in process of intra prediction.The proposed architecture can reduce external memory access by optimized internal buffer.
