In this paper, we consider the problems of data sharing between multiple distrusted authorities. Prior solutions rely on trusted third parties such as CAs, or are susceptible to collusion between malicious authorities...In this paper, we consider the problems of data sharing between multiple distrusted authorities. Prior solutions rely on trusted third parties such as CAs, or are susceptible to collusion between malicious authorities, which can comprise the security of honest ones. In this paper, we propose a new multi-authority data sharing scheme - Decen- tralized Multi-Authority ABE （DMA）, which is derived from CP-ABE that is resilient to these types of misbehavior. Our system distin- guishes between a data owner （DO） principal and attribute authorities （AAs）： the DO owns the data but allows AAs to arbitrate access by providing attribute labels to users. The data is protected by policy encryption over these attributes. Unlike prior systems, attributes generated by AAs are not user-specific, and neither is the system susceptible to collusion between users who try to escalate their access by sharing keys. We prove our scherne correct under the Decisional Bilinear Diffie-Hellman （DBDH） assumption; we also include a com- plete end-to-end implementation that demon- strates the practical efficacy of our technique.展开更多
A novel operation mechanism of capacitorless SOl-DRAM （silicon on insulator dynamic random access memory） cell using impact ionization and GIDL （gated-induce drain leakage） effects for write ＂1＂ operation was pr...A novel operation mechanism of capacitorless SOl-DRAM （silicon on insulator dynamic random access memory） cell using impact ionization and GIDL （gated-induce drain leakage） effects for write ＂1＂ operation was proposed. The conventional capacitorless DRAM cell with single charge generating effect is either high speed or low power, while the proposed DG-FinFET （double-gate fin field effect transistor） cell employs the efficient integration of impact ionization and GIDL effects by coupling the front and back gates with optimal body doping profile and proper bias conditions, yielding high speed low power performance. The simulation results demonstrate ideal characteristics in both cell operations and power consumption. Low power consumption is achieved by using GIDL current at 0. luA when the coupling between the front and back gates restrains the impact ionization current in the first phase. The write operation of the cell is within Ins attributed to significant current of the impact ionization effect in the second phase. By shortening second phase, power consumption could be further decreased. The ratio of read ＂1＂ and read ＂0＂ current is more than 9.38E5. Moreover, the cell has great retention characteristics.展开更多
Polar coded sparse code multiple access(SCMA) system is conceived in this paper. A simple but new iterative multiuser detection framework is proposed, which consists of a message passing algorithm(MPA) based multiuser...Polar coded sparse code multiple access(SCMA) system is conceived in this paper. A simple but new iterative multiuser detection framework is proposed, which consists of a message passing algorithm(MPA) based multiuser detector and a soft-input soft-output(SISO) successive cancellation(SC) polar decoder. In particular, the SISO polar decoding process is realized by a specifically designed soft re-encoder, which is concatenated to the original SC decoder. This soft re-encoder is capable of reconstructing the soft information of the entire polar codeword based on previously detected log-likelihood ratios(LLRs) of information bits. Benefiting from the soft re-encoding algorithm, the resultant iterative detection strategy is able to obtain a salient coding gain. Our simulation results demonstrate that significant improvement in error performance is achieved by the proposed polar-coded SCMA in additive white Gaussian noise(AWGN) channels, where the performance of the conventional SISO belief propagation(BP) polar decoder aided SCMA, the turbo coded SCMA and the low-density parity-check(LDPC) coded SCMA are employed as benchmarks.展开更多
A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power ga...A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.展开更多
The IEEE 802. 16 standard specifies the air interface of wireless metropolitan area network （WMAN）, and aims to provide wireless broadband access for integrated voice and video services. This paper presents the effi...The IEEE 802. 16 standard specifies the air interface of wireless metropolitan area network （WMAN）, and aims to provide wireless broadband access for integrated voice and video services. This paper presents the efficient design and implementation of fast Frouier transform （FFT） and inverse fast Frouier transform （IFFT） for the application in IEEE 802. 16d orthogoual frequency division multiplexing （OFDM） system. In this design, a novel pipeline structure for the branch of butterfly unit （BU） is proposed, which can improve the processing symbol rate by adding the number of branch flexibly. The symmetrical ping-pang structure of random access memory （RAM） is performed to increase the system throughput. Simulation results reveal that only with 1 branch of BU, the proposed FFF/IFFT design can almost achieve the maximum bandwidth requirement of IEEE 802. 16d OFDM system. And this design has been verified by FPGA and successfully implemented in the prototype of WiMAX transceiver.展开更多
The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）,...The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.展开更多
we have developed ferroelectric capacitor fabrication technique to realize low-voltage and high-density ferroelectric random access memory （FRAM）. High temperature deposited IrOxtop electrode reveals high crystallin...we have developed ferroelectric capacitor fabrication technique to realize low-voltage and high-density ferroelectric random access memory （FRAM）. High temperature deposited IrOxtop electrode reveals high crystalline quality which drastically reduces the degradation of ferroelectric film by preventing hydrogen diffusion into ferroelectric film. This improvement enables us to commercialize highly-reliable 1T 1C FRAM with memory density of 4 Mb or larger.展开更多
With the newly proposed Global Ocean Observing Integration, ocean observing scope has been expanded from the region to the global, therefore the need of large-scale ocean observing system integration has become more a...With the newly proposed Global Ocean Observing Integration, ocean observing scope has been expanded from the region to the global, therefore the need of large-scale ocean observing system integration has become more and more urgent. Currently, ocean observing systems enabled ocean sensor networks are commonly developed by different organizations using specific technologies and platforms, which brings several challenges in ocean observing instrument （OOI） access and ocean observing system seamless integration. Furthermore, the development of ocean observing systems often suffers from low efficiency due to the complex prograrmning and debugging process. To solve these problems, a novel model, Complex Virtual Instrument （CVI） Model, is proposed. The model provides formal definitions on observing instrument description file, CVI description file, model calculation method, development model and interaction standard. In addition, this model establishes mathematical expressions of two model calculation operations, meanwhile builds the mapping relationship between observing instrument description file and CVI description file. The CVI based on the new model can achieve automatic access to different OOIs, seamless integration and communication for heterogeneous environments, and further implement standardized data access and management for the global unified ocean observing network. Throughout the development, integration and application of such CVI, the rationality and feasibility of the model have been evaluated. The results confirm that the proposed model can effectively implement heterogeneous system integration, improve development efficiency, make full usage of reusable components, reduce development cost, and enhance overall software system quality. We believe that our new model has great significance to promote the large-scale ocean observing system integration.展开更多
SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programm...SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programmable chip) development. However, as the configuration memory and logic memory of the SRAM-based FPGA are highly susceptible to SEUs(single-event upsets) in deep space, it is a challenge to design and implement a highly reliable FPGA-based system for spacecraft, and no practical architecture has been proposed. In this paper, a new architecture for a reliable and reconfigurable FPGAbased computer in a highly critical GNC(guidance navigation and control) system is proposed. To mitigate the effect of an SEU on the system, multi-layer reconfiguration and multi-layer TMR(triple module redundancy) techniques are proposed, with a reliable reconfigurable real-time operating system(Space OS) managing the system level fault tolerance of the computer in the architecture. The proposed architecture for the reconfigurable FPGA-based computer has been implemented with COTS(commercial off the shelf) FPGA and has firstly been applied to the GNC system of a circumlunar return and reentry flight vehicle. The in-orbit results show that the proposed architecture is capable of meeting the requirements of high reliability and high availability, and can provide the expressive varying functionality and runtime flexibility for an FPGA-based GNC computer in deep space.展开更多
Resistive switching random access memories(RRAM)have been considered to be promising for future information technology with applications for non-volatile memory,logic circuits and neuromorphic computing.Key performanc...Resistive switching random access memories(RRAM)have been considered to be promising for future information technology with applications for non-volatile memory,logic circuits and neuromorphic computing.Key performances of those resistive devices are approaching the realistic levels for production.In this paper,we review the progress of valence change type memories,including relevant work reported by our group.Both electrode engineering and in-situ transmission electron microscopy(TEM)high-resolution observation have been implemented to reveal the influence of migration of oxygen anions/vacancies on the resistive switching effect.The understanding of resistive memory mechanism is significantly important for device applications.展开更多
Monte Carlo simulation results are reported on the single event upset(SEU) triggered by the direct ionization effect of low-energy proton. The SEU cross-sections on the 45 nm static random access memory(SRAM) were com...Monte Carlo simulation results are reported on the single event upset(SEU) triggered by the direct ionization effect of low-energy proton. The SEU cross-sections on the 45 nm static random access memory(SRAM) were compared with previous research work, which not only validated the simulation approach used herein, but also exposed the existence of saturated cross-section and the multiple bit upsets(MBUs) when the incident energy was less than 1 MeV. Additionally, it was observed that the saturated cross-section and MBUs are involved with energy loss and critical charge. The amount of deposited charge and the distribution with respect to the critical charge as the supplemental evidence are discussed.展开更多
基金supported by the National Natural Science Foundation of China under grant 61402160Hunan Provincial Natural Science Foundation of China under grant 2016JJ3043Open Funding for Universities in Hunan Province under grant 14K023
文摘In this paper, we consider the problems of data sharing between multiple distrusted authorities. Prior solutions rely on trusted third parties such as CAs, or are susceptible to collusion between malicious authorities, which can comprise the security of honest ones. In this paper, we propose a new multi-authority data sharing scheme - Decen- tralized Multi-Authority ABE （DMA）, which is derived from CP-ABE that is resilient to these types of misbehavior. Our system distin- guishes between a data owner （DO） principal and attribute authorities （AAs）： the DO owns the data but allows AAs to arbitrate access by providing attribute labels to users. The data is protected by policy encryption over these attributes. Unlike prior systems, attributes generated by AAs are not user-specific, and neither is the system susceptible to collusion between users who try to escalate their access by sharing keys. We prove our scherne correct under the Decisional Bilinear Diffie-Hellman （DBDH） assumption; we also include a com- plete end-to-end implementation that demon- strates the practical efficacy of our technique.
文摘A novel operation mechanism of capacitorless SOl-DRAM （silicon on insulator dynamic random access memory） cell using impact ionization and GIDL （gated-induce drain leakage） effects for write ＂1＂ operation was proposed. The conventional capacitorless DRAM cell with single charge generating effect is either high speed or low power, while the proposed DG-FinFET （double-gate fin field effect transistor） cell employs the efficient integration of impact ionization and GIDL effects by coupling the front and back gates with optimal body doping profile and proper bias conditions, yielding high speed low power performance. The simulation results demonstrate ideal characteristics in both cell operations and power consumption. Low power consumption is achieved by using GIDL current at 0. luA when the coupling between the front and back gates restrains the impact ionization current in the first phase. The write operation of the cell is within Ins attributed to significant current of the impact ionization effect in the second phase. By shortening second phase, power consumption could be further decreased. The ratio of read ＂1＂ and read ＂0＂ current is more than 9.38E5. Moreover, the cell has great retention characteristics.
基金supported in part by National Natural Science Foundation of China (no. 61571373, no. 61501383, no. U1734209, no. U1709219)in part by Key International Cooperation Project of Sichuan Province (no. 2017HH0002)+2 种基金in part by Marie Curie Fellowship (no. 792406)in part by the National Science and Technology Major Project under Grant 2016ZX03001018-002in part by NSFC China-Swedish project (no. 6161101297)
文摘Polar coded sparse code multiple access(SCMA) system is conceived in this paper. A simple but new iterative multiuser detection framework is proposed, which consists of a message passing algorithm(MPA) based multiuser detector and a soft-input soft-output(SISO) successive cancellation(SC) polar decoder. In particular, the SISO polar decoding process is realized by a specifically designed soft re-encoder, which is concatenated to the original SC decoder. This soft re-encoder is capable of reconstructing the soft information of the entire polar codeword based on previously detected log-likelihood ratios(LLRs) of information bits. Benefiting from the soft re-encoding algorithm, the resultant iterative detection strategy is able to obtain a salient coding gain. Our simulation results demonstrate that significant improvement in error performance is achieved by the proposed polar-coded SCMA in additive white Gaussian noise(AWGN) channels, where the performance of the conventional SISO belief propagation(BP) polar decoder aided SCMA, the turbo coded SCMA and the low-density parity-check(LDPC) coded SCMA are employed as benchmarks.
基金Projects(60873016, 61170083) supported by the National Natural Science Foundation of ChinaProject(20114307110001) supported by the Doctoral Fund of Ministry of Education of China
文摘A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.
基金Sponsored by the National Natural Science Foundation of China(Grant No.60425413)
文摘The IEEE 802. 16 standard specifies the air interface of wireless metropolitan area network （WMAN）, and aims to provide wireless broadband access for integrated voice and video services. This paper presents the efficient design and implementation of fast Frouier transform （FFT） and inverse fast Frouier transform （IFFT） for the application in IEEE 802. 16d orthogoual frequency division multiplexing （OFDM） system. In this design, a novel pipeline structure for the branch of butterfly unit （BU） is proposed, which can improve the processing symbol rate by adding the number of branch flexibly. The symmetrical ping-pang structure of random access memory （RAM） is performed to increase the system throughput. Simulation results reveal that only with 1 branch of BU, the proposed FFF/IFFT design can almost achieve the maximum bandwidth requirement of IEEE 802. 16d OFDM system. And this design has been verified by FPGA and successfully implemented in the prototype of WiMAX transceiver.
基金supported by the Second Stage of Brain Korea 21 Projectsfinancially supported by Changwon National University in 2011-2013
文摘The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.
文摘we have developed ferroelectric capacitor fabrication technique to realize low-voltage and high-density ferroelectric random access memory （FRAM）. High temperature deposited IrOxtop electrode reveals high crystalline quality which drastically reduces the degradation of ferroelectric film by preventing hydrogen diffusion into ferroelectric film. This improvement enables us to commercialize highly-reliable 1T 1C FRAM with memory density of 4 Mb or larger.
基金supported by the National Natural Science Foundation of China(Nos.41606112,61103196,61379127,61379128)the National High Technology Research and Development Program 863(No.2013AA09A506)
文摘With the newly proposed Global Ocean Observing Integration, ocean observing scope has been expanded from the region to the global, therefore the need of large-scale ocean observing system integration has become more and more urgent. Currently, ocean observing systems enabled ocean sensor networks are commonly developed by different organizations using specific technologies and platforms, which brings several challenges in ocean observing instrument （OOI） access and ocean observing system seamless integration. Furthermore, the development of ocean observing systems often suffers from low efficiency due to the complex prograrmning and debugging process. To solve these problems, a novel model, Complex Virtual Instrument （CVI） Model, is proposed. The model provides formal definitions on observing instrument description file, CVI description file, model calculation method, development model and interaction standard. In addition, this model establishes mathematical expressions of two model calculation operations, meanwhile builds the mapping relationship between observing instrument description file and CVI description file. The CVI based on the new model can achieve automatic access to different OOIs, seamless integration and communication for heterogeneous environments, and further implement standardized data access and management for the global unified ocean observing network. Throughout the development, integration and application of such CVI, the rationality and feasibility of the model have been evaluated. The results confirm that the proposed model can effectively implement heterogeneous system integration, improve development efficiency, make full usage of reusable components, reduce development cost, and enhance overall software system quality. We believe that our new model has great significance to promote the large-scale ocean observing system integration.
基金supported by the Major Special Projects on National Medium and Long-term Science and Technology Development Planning
文摘SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programmable chip) development. However, as the configuration memory and logic memory of the SRAM-based FPGA are highly susceptible to SEUs(single-event upsets) in deep space, it is a challenge to design and implement a highly reliable FPGA-based system for spacecraft, and no practical architecture has been proposed. In this paper, a new architecture for a reliable and reconfigurable FPGAbased computer in a highly critical GNC(guidance navigation and control) system is proposed. To mitigate the effect of an SEU on the system, multi-layer reconfiguration and multi-layer TMR(triple module redundancy) techniques are proposed, with a reliable reconfigurable real-time operating system(Space OS) managing the system level fault tolerance of the computer in the architecture. The proposed architecture for the reconfigurable FPGA-based computer has been implemented with COTS(commercial off the shelf) FPGA and has firstly been applied to the GNC system of a circumlunar return and reentry flight vehicle. The in-orbit results show that the proposed architecture is capable of meeting the requirements of high reliability and high availability, and can provide the expressive varying functionality and runtime flexibility for an FPGA-based GNC computer in deep space.
文摘Resistive switching random access memories(RRAM)have been considered to be promising for future information technology with applications for non-volatile memory,logic circuits and neuromorphic computing.Key performances of those resistive devices are approaching the realistic levels for production.In this paper,we review the progress of valence change type memories,including relevant work reported by our group.Both electrode engineering and in-situ transmission electron microscopy(TEM)high-resolution observation have been implemented to reveal the influence of migration of oxygen anions/vacancies on the resistive switching effect.The understanding of resistive memory mechanism is significantly important for device applications.
基金supported by the National Natural Science Foundation of China(Grant Nos.11179003,10975164,10805062 and 11005134)
文摘Monte Carlo simulation results are reported on the single event upset(SEU) triggered by the direct ionization effect of low-energy proton. The SEU cross-sections on the 45 nm static random access memory(SRAM) were compared with previous research work, which not only validated the simulation approach used herein, but also exposed the existence of saturated cross-section and the multiple bit upsets(MBUs) when the incident energy was less than 1 MeV. Additionally, it was observed that the saturated cross-section and MBUs are involved with energy loss and critical charge. The amount of deposited charge and the distribution with respect to the critical charge as the supplemental evidence are discussed.
