水下弹丸结构参数的优化方法

介绍了弹丸的运动模型并引入了速度衰减距离 a的概念 ,由于衰减距离 a在水介质性质因素不变的情况下 ,只与弹丸结构有关 ,因此 ,可以通过比较不同结构的弹丸的 a值来优化弹丸结构。文中将弹丸分为四种类型 ,通过大量的实验得出了存速能力最强的结构参数。

内置式预制破片设计

为实现弹丸威力与加工成本的合理匹配,用ANSYS的AutoDyn模块,采用数值仿真方法计算内置式预制破片的初始速度、飞散偏转角、衰减因数和存速能力等以及工艺方面的初始参数,优选出合理的破片大小和形状.试验表明优选得到的方案是可行的.

提高杀伤战斗部威力的技术途径研究

目的 研究提高杀伤战斗部威力的技术途径． 方法 应用弹道发射枪发射不同质量与直径的钢和重金属钨破片侵彻靶板， 测定破片的着速， 并比较其侵彻性能． 结果 根据测得的破片速度及侵彻性能的试验结果， 可以确定重金属破片具有非常优越的侵彻性能． 结论 当战场上目标的防护能力加强后， 在导弹。

尾翼弹高低空气动特性仿真及外弹道计算

对不同气象条件下的尾翼弹进行气动特性数值仿真,由Matlab拟合得到阻力系数随海拔高度、马赫数变化的公式并进行了各海拔高度处的外弹道计算。结果表明:在全声速范围内,相同马赫数处,阻力系数随着海拔高度的增加而增大,且基本为线性关系;在同一海拔高度处,阻力系数随着马赫数的变化规律相同;在相同射角,相同初速下,不同海拔高度处发射的尾翼弹的弹道轨迹、存速、弹道倾角变化较大,弹体存速随着海拔高度的增加而增加,弹道高,弹道倾角随着海拔高度的增加而下降,因此需考虑海拔高度对弹道参数的影响。

Database-oriented storage based on LMDB and linear octree for massive block model

Data organization requires high efficiency for large amount of data applied in the digital mine system. A new method of storing massive data of block model is proposed to meet the characteristics of the database, including ACID-compliant, concurrency support, data sharing, and efficient access. Each block model is organized by linear octree, stored in LMDB（lightning memory-mapped database）. Geological attribute can be queried at any point of 3D space by comparison algorithm of location code and conversion algorithm from address code of geometry space to location code of storage. The performance and robustness of querying geological attribute at 3D spatial region are enhanced greatly by the transformation from 3D to 2D and the method of 2D grid scanning to screen the inner and outer points. Experimental results showed that this method can access the massive data of block model, meeting the database characteristics. The method with LMDB is at least 3 times faster than that with etree, especially when it is used to read. In addition, the larger the amount of data is processed, the more efficient the method would be.

20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS

A 1 ：2 demultiplexer is designed and realized in standard 0. 18μm CMOS technology. A novel high-speed and low-voltage latch is used to realize the core circuit cell. Compared to the traditional source-coupled FET logic structure latch, its power supply voltage is lower and the speed is faster. In addition, the negative feedback is used in the buffer circuit to widen its bandwidth. Measurement results show that the chip can work at the data rate of 20Gb/ s. The supply voltage is 1.8V and the current,including the buffer circuit, is 72mA.

Low Voltage Flash Memory Cells Using SiGe Quantum Dots for Enhancing F-N Tunneling

A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing. Simulation results indicate the new structure provides high speed and reliability. Experimental results show that the operation voltage can be as much as 4V less than that of conventional full F-N tunneling NAND memory cells. Memory cells with the proposed structure can achieve higher speed, lower voltage, and higher reliability.

A method based on vector type for sparse storage and quick access to projection matrix

For sparse storage and quick access to projection matrix based on vector type, this paper proposes a method to solve the problems of the repetitive computation of projection coefficient, the large space occupation and low retrieval efficiency of projection matrix in iterative reconstruction algorithms, which calculates only once the projection coefficient and stores the data sparsely in binary format based on the variable size of library vector type. In the iterative reconstruction process, these binary files are accessed iteratively and the vector type is used to quickly obtain projection coefficients of each ray. The results of the experiments show that the method reduces the memory space occupation of the projection matrix and the computation of projection coefficient in iterative process, and accelerates the reconstruction speed.

A Novel Non-Planar Cell Structure for Flash Memory

Proposed herein is a novel non planar cell structure for flash memory which has been fabricated to achieve high programming speed with low operating voltage.This memory cell preserves a simple stacked gate structure which only requires an additional masking step to form the novel structure in the channel.For the cell of the 1 2μm gate length,the programming speed of 43μs under the measuring condition of V g=15V, V d=5V,and the erasing time of 24ms under V g=-5V, V s=8V are obtained.The programming speed is faster than that of the conventional planar cell structure.This superior programming speed makes it suitable for high speed application.

SCDI Flash Memory Device Ⅰ: Simulation and Analysis

Step channel direct injection(SCDI)flash memory device which had been developed changes the hot carrier injection method by making a shallow step in the middle of channel .Therefore high speed for programming,high efficiency for injection,and lower working voltage are obtained.Simulation and analysis for the proposed SCDI structure device are done and an optimization scheme to improve the utmost performance of SCDI device is given...

SCDI Flash Memory Device Ⅱ:Experiments and Characteristics

Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed of SCDI device is 42μs.Under the condition of V g=-8V, V s=8V,the erasing speed is 24ms.Compared with the same size of conventional flash memory device whose corresponding parameters are 500μs and 24ms,respectively,the performance of SCDI device is remarkably improved.During manufacturing of SCDI device,the key technologies are to make the shallow step with appropriate depth and angle,along with eliminating the etch damage during the process of Si 3N 4 spacer.

Design of high-speed signal acquisition system and analysis of signal integrity

The device is used for the test on the fuze detonating time according to the initial velocity of the projectile and the altitude and speed of enemy aircraft flight. For the special requirements of the high-speed signal acquisition in the process, the characteristics of the measured signal are analyzed. The system is investigated in chip selection, signal transmission, signal processing, signal storage, post-production PCB design, etc. The appropriate measures and solutions which affect the integrity and accuracy of the signal in each process are proposed. The rules for the layout of the device and wiring are made. The result show that the measurement values are accurate without loss of data.

A Low-Power Super-Performance Four-Way Set-Associative CMOS Cache Memory

A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...

Design of RTD-Based TSRAM

A RTD-based TSRAM cell is introduced.The mechanism of different types of access transistors in this cell is described and NMOS is found most suitable from consideration of the cell size and power consumption.The architecture of a TSRAM system is presented.Simulation results show that the RTD-based TSRAM has advanced characteristics of small area,low power,and high speed.

A P2P streaming service architecture with distributed caching

Multimedia streaming served through peer-to-peer (P2P) networks is booming nowadays. However, the end-to-end streaming quality is generally unstable due to the variability of the state of serve-peers. On the other hand, proxy caching is a bandwidth-efficient scheme for streaming over the Internet, whereas it is a substantially expensive method needing dedicated powerful proxy servers. In this paper, we present a P2P cooperative streaming architecture combined with the advantages of both P2P networks and multimedia proxy caching techniques to improve the streaming quality of participating clients. In this frame- work, a client will simultaneously retrieve contents from the server and other peers that have viewed and cached the same title before. In the meantime, the client will also selectively cache the aggregated video content so as to serve still future clients. The associate protocol to facilitate the multi-path streaming and a distributed utility-based partial caching scheme are detailedly dis- cussed. We demonstrate the effectiveness of this proposed architecture through extensive simulation experiments on large, Inter- net-like topologies.

Low-Complexity Detection and Decoding Scheme for LDPC-Coded MLC NAND Flash Memory

With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.

AN EMPIRICAL STUDY ON USER ACCESS TO ENTERTAINMENT STREAMING MEDIA

Due to large size and different popularity for different part of the video, most proxy caches for streaming medias cache only a part of the video. Thus, an accurate understanding on the internal popularity distribution of media objects in streaming applications is very important for the development of efficient cache mechanisms. This letter shows that the internal popularity of popular streaming media obeys a k-transformed Zipf-like distribution through analyzing two 6-month long traces recorded at different streaming video servers of an entertainment video-on-demand provider. This empirical model can be used to design an efficient cach- ing algorithm.

Monitoring nearest neighbor queries with cache strategies

The problem of continuously monitoring multiple K-nearest neighbor (K-NN) queries with dynamic object and query dataset is valuable for many location-based applications. A practical method is to partition the data space into grid cells, with both object and query table being indexed by this grid structure, while solving the problem by periodically joining cells of objects with queries having their influence regions intersecting the cells. In the worst case, all cells of objects will be accessed once. Object and query cache strategies are proposed to further reduce the I/O cost. With object cache strategy, queries remaining static in current processing cycle seldom need I/O cost, they can be returned quickly. The main I/O cost comes from moving queries, the query cache strategy is used to restrict their search-regions, which uses current results of queries in the main memory buffer. The queries can share not only the accessing of object pages, but also their influence regions. Theoretical analysis of the expected I/O cost is presented, with the I/O cost being about 40% that of the SEA-CNN method in the experiment results.

Dynamic evolution of shear rate-dependent behavior of rock discontinuity under shearing condition

Rock blocks sliding along discontinuities can cause serious disasters,such as landslides,earthquakes,or rock bursts.The shear rate-dependent behavior is a typical time-dependent behavior of a rock discontinuity,and it is closely related to the stability of a rock block.To further study the shear rate-dependent behavior of rock discontinuities,shear tests with alternating shear rates(SASRs)were conducted on rock discontinuities with various surface morphologies.The dynamic evolution of the shear rate dependency was studied in detail based on the shear test results,and three stages were identified with respect to the shear stress and shear deformation states.The test results revealed that dynamic changes in shear stiffness and the energy storage abilities of the rock discontinuities occurred in relation to the shear rate-dependent behavior of crack growth,which increased with an increase in normal stress and/or the joint roughness coefficient.The stage of decreasing shear stiffness corresponded to a stage of noticeable shear rate-dependency,and the shear rate was found to have no influence on the initial crack stress.

Packet Cache-Forward Method Based on Improved Bayesian Outlier Detection for Mobile Handover in Satellite Networks

In this paper, we propose a Packet Cache-Forward(PCF) method based on improved Bayesian outlier detection to eliminate out-of-order packets caused by transmission path drastically degradation during handover events in the moving satellite networks, for improving the performance of TCP. The proposed method uses an access node satellite to cache all received packets in a short time when handover occurs and forward them out in order. To calculate the cache time accurately, this paper establishes the Bayesian based mixture model for detecting delay outliers of the entire handover scheme. In view of the outliers' misjudgment, an updated classification threshold and the sliding window has been suggested to correct category collections and model parameters for the purpose of quickly identifying exact compensation delay in the varied network load statuses. Simulation shows that, comparing to average processing delay detection method, the average accuracy rate was scaled up by about 4.0%, and there is about 5.5% cut in error rate in the meantime. It also behaves well even though testing with big dataset. Benefiting from the advantage of the proposed scheme in terms of performance, comparing to conventional independent handover and network controlled synchronizedhandover in simulated LEO satellite networks, the proposed independent handover with PCF eliminates packet out-of-order issue to get better improvement on congestion window. Eventually the average delay decreases more than 70% and TCP performance has improved more than 300%.