利用V ISUAL C++开发环境设计一个基于U N ICODE字符集的多语言应用程序。为方便使用,设计了实现多语言实时切换的应用程序。实现原理是将各种语言资源脚本用U N ICODE字符集保存,并封装到“卫星”资源动态链接库中,通过实时动态地加载...利用V ISUAL C++开发环境设计一个基于U N ICODE字符集的多语言应用程序。为方便使用,设计了实现多语言实时切换的应用程序。实现原理是将各种语言资源脚本用U N ICODE字符集保存,并封装到“卫星”资源动态链接库中,通过实时动态地加载不同语言动态库,实现了软件界面的多语言实时切换。展开更多
Rigorous modeling could improve the correctness and reduce cost in embedded real-time system development for models could be verified. Tools are needed for rigorous modeling of embedded real-time system. UML is an ind...Rigorous modeling could improve the correctness and reduce cost in embedded real-time system development for models could be verified. Tools are needed for rigorous modeling of embedded real-time system. UML is an industrial standard modeling language which provides a powerful expressi-veness, intuitive and easy to use interface to model. UML is widely accepted by software developer. However, for lack of precisely defined semantics, especially on the dynamic diagrams, UML model is hard to be verified. PVS is a general formal method which provides a high-order logic specification language and integrated with model checking and theorem proving tools. Combining the widely used UML with PVS, this paper provides a novel modeling and verification approach for embedded real-time system. In this approach, we provide 1) a timed extended UML statechart for modeling dynamic behavior of an embedded real-time system; 2) an approach to capture timed automata based semantics from timed statechart; and 3) an algorithm to generate a finite state model expressed in PVS specification for model checking. The benefits of our approach include flexible and friendly in modeling, extendable in forma-lization and verification content, and better performance. Time constraints are modeled and verified and it’s a highlight of this paper.展开更多
文摘Rigorous modeling could improve the correctness and reduce cost in embedded real-time system development for models could be verified. Tools are needed for rigorous modeling of embedded real-time system. UML is an industrial standard modeling language which provides a powerful expressi-veness, intuitive and easy to use interface to model. UML is widely accepted by software developer. However, for lack of precisely defined semantics, especially on the dynamic diagrams, UML model is hard to be verified. PVS is a general formal method which provides a high-order logic specification language and integrated with model checking and theorem proving tools. Combining the widely used UML with PVS, this paper provides a novel modeling and verification approach for embedded real-time system. In this approach, we provide 1) a timed extended UML statechart for modeling dynamic behavior of an embedded real-time system; 2) an approach to capture timed automata based semantics from timed statechart; and 3) an algorithm to generate a finite state model expressed in PVS specification for model checking. The benefits of our approach include flexible and friendly in modeling, extendable in forma-lization and verification content, and better performance. Time constraints are modeled and verified and it’s a highlight of this paper.
