CHAOTIC TRANSDUCER

Utilizing the character of chaos, the sensitivity to the initial conditions, the concept and the structure of so-called chaotic transducer based on Tent map is provided in this paper creatively. The possibility of applying the basic theory of symbolic dynamics to the measurement is presented and proved. Then, the theoretical model of chaotic transducer is realized by using the switched capacitor and the basic experimental results are given. The transducer has such characters as high sensitivity, resolution, the simple structure and combining signal amplification with A/D. The new area of the application of chaos is exploited. Meanwhile, it provides a new method of exploring the structure of new type transducer.

A 2GHz Low Power Differentially Tuned CMOS Monolithic LC-VCO

A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process. The VCO has a 16.15% tuning range （from 1. 8998 to 2. 2335GHz） through a combination of analog and digital tuning techniques （4-bit binary switch-capacitor array）. The measured phase noise is - 118.17dBc/Hz at a 1MHz offset from a 2. 158GHz carrier. With the presented improved switch,the phase noise varies no more than 3dB at different digital control bits. The phase noise changes only by about 2dB in the tuning range because of the pn-junctions as the varactors. The VCO draws a current of about 2. lmA from a 1.8V power supply and works normally with a 1.5V power supply.

A Novel Regulation Technique and Its Application to Design of Embedded SC DC-DC Converters

An optimized design of the monolithic switched capacitor DC-DC converter is presented.The general topologic circuit and its basic operating principles are discussed theoretically.Circuit equivalent resistance regulation method is proposed as a feasible method to design the on-chip converters.N-channel MOSFETs,instead of Schottky diodes,are used as the diodes in the converters because of their processing compatibility in monolithic fabrication.One more manufacture step,however,is expected to adjust the threshold voltage of the MOSFETs for improving output characteristics of the converters.As an example,a step-up switched-capacitor converter is fabricated in a 2μm p-well double-poly single-metal CMOS technology with breakdown voltage of 15V.Test results indicate that a single sampling cell with 0.4mm 2 of die size can deliver energy up to 0.63mW at 5V output under the condition of 3V input.Efficiency of the tested sample is 68% at 9.8MHz switching frequency...

A 16 bit Stereo Audio ΣΔ A/D Converter

A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a high order single stage ∑△ modulator is also proposed. A new multistage comb filter is used for the front end decimation filter. The ∑△ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB. The ADC was implemented in 0. 5μm 5V CMOS technology. The chip die area occupies only 4. 1mm × 2.4mm and dissipates 90mW.

Improving Characteristics of Integrated Switched-Capacitor DC-DC Converter by CMOS Technology

An integrated 3.3V/1.2V SC DC-DC converter operating under 10MHz with a fixed duty radio of 0.5 is presented.To improve the output current of the converter,CMOS technology is adopted to fabricate the switching devices,and mutually compensatory circuitry technology is also employed to double the output current furthermore.The simulation results using Hspice simulation software,show that the output currents of a single unit circuit and two unit circuits connected in a mutually compensatory manner of the improved converter is about 12.5mA and 26mA,respectively.The power conversion efficiency of the mutually compensatory circuit can amount to 73%,while its output voltage ripple is less than 1.5%.The converter is fabricated in standard Rohm 0.35μm CMOS technology in Tokyo University of Japan.The test result indicates that the output current of 9.8mA can be obtained from a single unit circuit of the improved converter.

捉猴记

中秋节这天,毋旺根开着新买的车,拉着妻儿,回老家猴山,看望父母。车刚停好,70多岁的父母就迎了上来。父亲摸着孙子的头一脸笑容：“这辆车是你刚买的？”“是我刚买的,省里搞车改,我没有专车坐了。”老父亲又说：“开自己的车回来,这就对了。村里人也不说咱开着公家车显摆了。”快到中午了,毋旺根带着一家人来到县城一家饭店,点了一桌菜。一家老小,有说有笑。

A Novel Sampling Switch Suitable for Low-Voltage Analog-to-Digital Converters

A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity resuiting from threshold voltage variation, which has not been accomplished in earlier low-voltage sampling switches. This is achieved by adopting a replica transistor with the same threshold voltage as the sampling transistor. The effectiveness of this technique is demonstrated by a prototype design of a sampling switch in 0. 35μm. The proposed sampling switch achieves a spurious free dynamic range of 111dB for a 0. 2MHz, 1.2Vp-p input signal, sampled at a rate of 2MS/s,about 18dB over the Bootstrapped switch. Also, the on-resistance variation is reduced by 90%. This method is especially useful for low-voltage, high resolution ADCs, which is a hot topic today.

A 4.8GHz CMOS Fully Integrated LC Balanced Oscillator with Symmetrical Noise Filter Technique and Large Tuning Range

This paper presents a fully integrated 4 8GHz VCO with an invention——symmetrical noise filter technique.This VCO,with relatively low phase noise and large tuning range of 716MHz,is fabricated with the 0 25μm SMIC CMOS process.The oscillator consumes 6mA from 2 5V supply.Another conventional VCO is also designed and simulated without symmetrical noise filter on the same process,which also consumes 6mA current and is with the same tuning.Simulation result describes that the first VCO’ phase noise is 6dBc/Hz better than the latter’s at the same offset frequency from 4 8GHz.Measured phase noise at 1MHz away from the carrier in this 4 8GHz VCO with symmetrical noise filter is -123 66dBc/Hz.This design is suitable for the usage in a phase locked loop and other consumer electronics.It is amenable for future technologies and allows easy porting to different CMOS manufacturing process.

Analysis and design of sigma-delta interface circuit for quartz flexural pendulum accelerometer

For the high resolution required in a digital interface circuit of an accelerometer used in feeble gravity measurement, a switched-capacitor （SC） sigma-delta modulator （SDM） is proposed. Based on the principle and the topology structure of the SDMs, the influence of oversampling ratio, bits of an internal quantizer and the cascaded structure on weak signal detecting precision is analyzed, and an ideal low-distortion SDM with a second-order 1-bit structure satisfying the high- resolution interface circuit of an accelerometer is designed. With the research on non-idealities of each SDM block in the SC circuit implementation and their impacts on power consumption, the realized parameters of low-power SDMs based on different bandwidths are devised and the power consumption of each SDM is estimated. Time-domain behavioral simulation is explored based on Simulink. The results demonstrate that a 21- bit resolution of the designed SDMs can be achieved on the premise of low power, and the parameters for the circuit implementation can be directed to the transistor-level circuit design.

"大腕儿"

提起赵本山、黄宏这些小品 演员,借句广告语来说:"地球人 都知道"。他们可是响当当的"大 腕儿"。今天,我写的"大腕儿", 虽然比不上他们,可在我们院子 里也算"当当响"了。一号大腕 儿,咱妈也:二号大腕儿,咱爸也; 三号大腕儿,在下是也。"一家三 口,三个’大腕儿’,这不是王婆 卖瓜,自卖自夸吗?"肯定有人这 么说。得了,我也甭吹了,还是请 各位看完小品再说吧！

“浪子”老爸

爸爸怎么会是“浪子”呢？事情还得从我上英语培训班开始说起。为了让我的英语成绩更上一层楼,妈妈毫不犹豫地替我报了周末的英语提高班,而老爸义不容辞地承担起接送我的任务。来到培训地点,等车停稳后,我便迫不及待地冲上了楼。而素有“工作狂”称号的老爸，为了避免忘记时间过来接我，决定在楼下等我。

拍戏,或是打一架 尼古拉斯·温丁·雷弗恩的电影方法论

雷弗恩是当今少有的"苦心经营"着暴力的导演。他的电影里,暴力元素总是被美化。各种技巧令暴戾的影像艺术化,令人神魂颠倒,但却美得合情合理。因此,你可以说他的电影是一种高档的垃圾,但这也是一种赞美,因为换句话说,这其实就是赤裸裸的"艺术掠夺"。

A wideband low-phase-noise LC VCO for DRM/DAB frequency synthesizer

The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply.

Capacitive Microwave MEMS Switch

A novel capacitive microwave MEMS switch with a silicon/metal/dielectric as a membrane is fabricated successfully by bonding and etching-stop process. Its principal, design, and fabricating process are described in detail. A patterned dielectric layer, Ta2O5, with dielectric constant of 24 is reached. Experiment results show this novel structure,where the switch＇s dielectric layer is not prepared on the transmission line, features very low insertion loss. The insertion loss is 0.06dB at 2GHz and lower than 0.5dB in the wider range from De up to 20GHz,especially when the transmission line metal is only 0. 5μm thick.

A High Linearity,13bit Pipelined CMOS ADC

A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.

An 80dB Dynamic Range ΣΔ Modulator for Low-IF GSM Receivers

A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits in standard 0. 6μm 2P2M CMOS technology. The modulator uses two balanced reference voltages of ±1V,and is driven by a single 26MHz clock signal. The measurement results show that,with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range,a 71.8dB peak SNDR,and a 73.9dB peak SNR in the signal bandwidth of 200kHz. The modulator dissipates 15mW static power from a single 5V supply.

In-package P/G planes analysis and optimization based on transmission matrix method

Power integrity (PI) has become a limiting factor for the chip's overall performance, and how to place in-package decoupling capacitors to improve a chip's PI performance has become a hot issue. In this paper, we propose an improved trans- mission matrix method (TMM) for fast decoupling capacitance allocation. An irregular grid partition mechanism is proposed, which helps speed up the impedance computation and complies better with the irregular power/ground (P/G) plane or planes with many vias and decoupling capacitors. Furthermore, we also ameliorate the computation procedure of the impedance matrix whenever decoupling capacitors are inserted or removed at specific ports. With the fast computation of impedance change, in-package decoupling capacitor allocation is done with an efficient change based method in the frequency domain. Experimental results show that our approach can gain about 5× speedup compared with a general TMM, and is efficient in restraining the noise on the P/G plane.

A NEW SWITCHED CAPACITOR RESONATOR AND ITS RESEARCH

In bandpass sigma delta modulator, resonator is the key block, This papcr proposed a new resonator which can simplify the circuit implementation when designing bandpass modulator with Iowpass prototype. The effect of finite gain, finite bandwidth, and path mismatch on the resonator is analyzed. The function of the proposed resonator and the devired equations about path mismatch have been verified by switched capacitor software SWITCAR.

Switched Capacitor Network Analysis by Means of TCM

The totally coded method (TCM) reveals the same objective law, which governs the gain calculating for signal flow graph as Mason formula does. This algorithm is carried out merely in the domain of code operation. Based on pure code algorithm, it is more efficient because figure searching is no longer necessary. The code-series ( CS ), which are organized from node association table, have the holoinformation nature, so that both the content and the sign of each gain-term can be determined via the coded method.The principle of this method is obvious and it is suited for computer programming. The capability of the computeraided analysis for Switched Capacitor (SCN) can be enhanced.

High Speed Column-Parallel CDS/ADC Circuit with Nonlinearity Compensation for CMOS Image Sensors

A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.