To cope with the ever-increasing susceptibility to transient fault in modern processors,a scheme called Tri-modular Redundantly and Simultaneously Threaded processor with Recovery is proposed,which provides transient ...To cope with the ever-increasing susceptibility to transient fault in modern processors,a scheme called Tri-modular Redundantly and Simultaneously Threaded processor with Recovery is proposed,which provides transient fault coverage and reconfiguration from partial permanent fault with high performance.Besides two redundant thread contexts,an arbitrator context is introduced to act as either arbitrator or ordinary thread,which can make better use of hardware resources.Its sphere of replication is reconfigurable and flexible in handling changing demands.The simulation with 11 SPEC2000 benchmarks shows that its performance outperforms SMT-Single by 21.5% on average,while maintaining flexibility and fault-tolerant capability.展开更多
The evolvable multiprocessor (EvoMP), as a novel multiprocessor system-on-chip (MPSoC) machine with evolvable task decomposition and scheduling, claims a major feature of low-cost and efficient fault tolerance. Non-ce...The evolvable multiprocessor (EvoMP), as a novel multiprocessor system-on-chip (MPSoC) machine with evolvable task decomposition and scheduling, claims a major feature of low-cost and efficient fault tolerance. Non-centralized control and adaptive distribution of the program among the available processors are two major capabilities of this platform, which remarkably help to achieve an efficient fault tolerance scheme. This letter presents the operational as well as architectural details of this fault tolerance scheme. In this method, when a processor becomes faulty, it will be eliminated of contribution in program execution in remaining run-time. This method also utilizes dynamic rescheduling capability of the system to achieve the maximum possible efficiency after processor reduction. The results confirm the efficiency and remarkable advantages of the proposed approach over common redundancy based techniques in similar systems.展开更多
基金Sponsored by the National Pre-research Foundation(Grant No.41316.1.2).
文摘To cope with the ever-increasing susceptibility to transient fault in modern processors,a scheme called Tri-modular Redundantly and Simultaneously Threaded processor with Recovery is proposed,which provides transient fault coverage and reconfiguration from partial permanent fault with high performance.Besides two redundant thread contexts,an arbitrator context is introduced to act as either arbitrator or ordinary thread,which can make better use of hardware resources.Its sphere of replication is reconfigurable and flexible in handling changing demands.The simulation with 11 SPEC2000 benchmarks shows that its performance outperforms SMT-Single by 21.5% on average,while maintaining flexibility and fault-tolerant capability.
文摘The evolvable multiprocessor (EvoMP), as a novel multiprocessor system-on-chip (MPSoC) machine with evolvable task decomposition and scheduling, claims a major feature of low-cost and efficient fault tolerance. Non-centralized control and adaptive distribution of the program among the available processors are two major capabilities of this platform, which remarkably help to achieve an efficient fault tolerance scheme. This letter presents the operational as well as architectural details of this fault tolerance scheme. In this method, when a processor becomes faulty, it will be eliminated of contribution in program execution in remaining run-time. This method also utilizes dynamic rescheduling capability of the system to achieve the maximum possible efficiency after processor reduction. The results confirm the efficiency and remarkable advantages of the proposed approach over common redundancy based techniques in similar systems.
