SRAM （Static RAM）-based FPGAs （Field Programmable Gate Arrays （FPGAs） have gained wide acceptance due to their on-line reconfigurable features. The growing demand for FPGAs has motivated semiconductor chip manufa...SRAM （Static RAM）-based FPGAs （Field Programmable Gate Arrays （FPGAs） have gained wide acceptance due to their on-line reconfigurable features. The growing demand for FPGAs has motivated semiconductor chip manufacturers to build more densely packed FPGAs with higher logic capacity. The downside of high density devices is that the probability of errors in such devices tends to increase. This paper proposes an FPGA architecture that is composed of an array of cells with built in error correction capability. Collectively a group of such cells can implement any logic function that is either registered or combinational. A cell is composed of three units： a logic block, a fault-tolerant address generator and a director unit. The logic block uses a look-up table to implement logic functions. The fault-tolerant address generator corrects any single bit error in the incoming data to the functional cell. The director block can transmit output data from the logic block to another cell located at its South, North, East or West, or to cells in all four directions. Thus a functional cell can also be used to route signals to other functional cells, thus avoiding any intricate network of interconnects, switching boxes, or routers commonly found in commercially available FPGAs.展开更多
Delay-Tolerant Networks (DTNs) are wireless networks that often experience temporary, even long-duration partitioning. Current DTN researches mainly focus on pure delay-tolerant networks that are extreme environments ...Delay-Tolerant Networks (DTNs) are wireless networks that often experience temporary, even long-duration partitioning. Current DTN researches mainly focus on pure delay-tolerant networks that are extreme environments within a limited application scope. It motivates the identification of a more reasonable and valuable DTN architecture, which can be applied in a wider range of environments to achieve interoperability between some networks suffering from frequent network partitioning, and other networks provided with stable and high speed Internet access. Such hybrid delay-tolerant networks have a lot of applications in real world. A novel and practical Cache-Assign-Forward (CAF) architecture is proposed as an appropriate approach to tie together such hybrid networks to achieve an efficient and flexible data communication. Based on CAF, we enhance the existing DTN routing protocols and apply them to complex hybrid delay-tolerant networks. Simulations show that CAF can improve DTN routing performance significantly in hybrid DTN environments.展开更多
基金Acknowledgement The first author was supported in part by the National Science Foundation, USA under Grant 0925080.
文摘SRAM （Static RAM）-based FPGAs （Field Programmable Gate Arrays （FPGAs） have gained wide acceptance due to their on-line reconfigurable features. The growing demand for FPGAs has motivated semiconductor chip manufacturers to build more densely packed FPGAs with higher logic capacity. The downside of high density devices is that the probability of errors in such devices tends to increase. This paper proposes an FPGA architecture that is composed of an array of cells with built in error correction capability. Collectively a group of such cells can implement any logic function that is either registered or combinational. A cell is composed of three units： a logic block, a fault-tolerant address generator and a director unit. The logic block uses a look-up table to implement logic functions. The fault-tolerant address generator corrects any single bit error in the incoming data to the functional cell. The director block can transmit output data from the logic block to another cell located at its South, North, East or West, or to cells in all four directions. Thus a functional cell can also be used to route signals to other functional cells, thus avoiding any intricate network of interconnects, switching boxes, or routers commonly found in commercially available FPGAs.
基金The authors would like to thank Prof. Xu Zhiwei and the re- viewers for their detailed reviews and constructive comments, which have helped improve the quality of this paper. This work was supported by the National Key Basic Research Program of China under Grant No. 2011CB302702 the Na- tional Natural Science Foundation of China under Grants No. 61132001, No. 61120106008, No. 61070187, No. 60970133, No. 61003225 the Beijing Nova Program.
文摘Delay-Tolerant Networks (DTNs) are wireless networks that often experience temporary, even long-duration partitioning. Current DTN researches mainly focus on pure delay-tolerant networks that are extreme environments within a limited application scope. It motivates the identification of a more reasonable and valuable DTN architecture, which can be applied in a wider range of environments to achieve interoperability between some networks suffering from frequent network partitioning, and other networks provided with stable and high speed Internet access. Such hybrid delay-tolerant networks have a lot of applications in real world. A novel and practical Cache-Assign-Forward (CAF) architecture is proposed as an appropriate approach to tie together such hybrid networks to achieve an efficient and flexible data communication. Based on CAF, we enhance the existing DTN routing protocols and apply them to complex hybrid delay-tolerant networks. Simulations show that CAF can improve DTN routing performance significantly in hybrid DTN environments.
