本方案设计的频率计由衰减电路、宽带通道放大器、整形电路、FPGA测量模块、STM32单片机最小系统组成。设计了一个放大倍数为40 d B的两级宽带通道放大器,将10 m V(有效值)的信号放大到1 V(有效值)左右。第一级使用OPA847实现了26 d B...本方案设计的频率计由衰减电路、宽带通道放大器、整形电路、FPGA测量模块、STM32单片机最小系统组成。设计了一个放大倍数为40 d B的两级宽带通道放大器,将10 m V(有效值)的信号放大到1 V(有效值)左右。第一级使用OPA847实现了26 d B的放大,第二级使用THS3201实现了14 d B的放大。当被测信号幅度较大时,使用衰减网络将被测信号衰减到10 m V左右。放大后的信号整形后产生相同频率的方波信号,使用Cyclone IV FPGA芯片实现等精度法测量频率、时间间隔和占空比。测量结果通过串口传给STM32单片机系统进行相关处理和显示。展开更多
In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz ...In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.展开更多
文摘本方案设计的频率计由衰减电路、宽带通道放大器、整形电路、FPGA测量模块、STM32单片机最小系统组成。设计了一个放大倍数为40 d B的两级宽带通道放大器,将10 m V(有效值)的信号放大到1 V(有效值)左右。第一级使用OPA847实现了26 d B的放大,第二级使用THS3201实现了14 d B的放大。当被测信号幅度较大时,使用衰减网络将被测信号衰减到10 m V左右。放大后的信号整形后产生相同频率的方波信号,使用Cyclone IV FPGA芯片实现等精度法测量频率、时间间隔和占空比。测量结果通过串口传给STM32单片机系统进行相关处理和显示。
基金supported by National 973 Program of China 2010CB327404National 863 Program of China 2011AA010202+2 种基金National Science and Technology Major Project of China 2012ZX03004004National Natural Science Foundation of China under grants 61101001,and 61204026Tsinghua University Initiative Scientific Research Program
文摘In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.
