Register transfer level mapping (RTLM) algorithm for technology mapping at RT level is presented,which supports current design methodologies using high level design and design reuse.The mapping rules implement a sou...Register transfer level mapping (RTLM) algorithm for technology mapping at RT level is presented,which supports current design methodologies using high level design and design reuse.The mapping rules implement a source ALU using target ALU.The source ALUs and the target ALUs are all represented by the general ALUs and the mapping rules are applied in the algorithm.The mapping rules are described in a table fashion.The graph clustering algorithm is a branch and bound algorithm based on the graph formulation of the mapping algorithm.The mapping algorithm suits well mapping of regularly structured data path.Comparisons are made between the experimental results generated by 1 greedy algorithm and graphclustering algorithm,showing the feasibility of presented algorithm.展开更多
基金supported in part by Estonian Science Foundation through grants 8478 and 7068European Commission projects FP7-2009-IST-4-248613 DIAMOND and FP7-REGPOT-2008-1 CREDESResearch Centre CEBE funded by EU Structural Funds
文摘Register transfer level mapping (RTLM) algorithm for technology mapping at RT level is presented,which supports current design methodologies using high level design and design reuse.The mapping rules implement a source ALU using target ALU.The source ALUs and the target ALUs are all represented by the general ALUs and the mapping rules are applied in the algorithm.The mapping rules are described in a table fashion.The graph clustering algorithm is a branch and bound algorithm based on the graph formulation of the mapping algorithm.The mapping algorithm suits well mapping of regularly structured data path.Comparisons are made between the experimental results generated by 1 greedy algorithm and graphclustering algorithm,showing the feasibility of presented algorithm.
