在MIPS,ALPHA,SPARC和PowerPC等体系结构中,对全局变量和静态变量的访问一般采用间接寻址的方式.由于变量地址和变量值不在同一数据段,使得数据访问的局部性不好.这样,每次访问变量地址会导致大量冗余的数据cache不命中访存操作.此外,...在MIPS,ALPHA,SPARC和PowerPC等体系结构中,对全局变量和静态变量的访问一般采用间接寻址的方式.由于变量地址和变量值不在同一数据段,使得数据访问的局部性不好.这样,每次访问变量地址会导致大量冗余的数据cache不命中访存操作.此外,这种寻址方式会产生两条连续的有数据依赖的操作,降低了程序的指令级并行性.提出了基于反馈信息的地址寄存器提升算法(address register promotion based on feedbacks,ARPF).该算法减少了对全局变量地址和静态变量地址的冗余访问,提高了程序的ILP(instruction level parallelism),同时避免了由于寄存器压力增加导致性能下降.在龙芯编译器①上实现了该算法.实验表明ARPF对SPEC CPU2000INT所有测试用例有1%～6%的性能提升.展开更多
本文结合 L S MPP嵌入式计算机图象匹配算法的设计与编程实践 ,对面向图象理解应用的 SIMD计算机减少存储类指令及其执行周期、控制寄存器的数量需求、基地址控制寄存器内容的保护、缓冲器的有关设计及图象阵列数据类型的设立等设计问...本文结合 L S MPP嵌入式计算机图象匹配算法的设计与编程实践 ,对面向图象理解应用的 SIMD计算机减少存储类指令及其执行周期、控制寄存器的数量需求、基地址控制寄存器内容的保护、缓冲器的有关设计及图象阵列数据类型的设立等设计问题进行了分析和讨论 ,提出的一些设计思想对于面向图象理解的类似展开更多
Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback sh...Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.展开更多
文摘在MIPS,ALPHA,SPARC和PowerPC等体系结构中,对全局变量和静态变量的访问一般采用间接寻址的方式.由于变量地址和变量值不在同一数据段,使得数据访问的局部性不好.这样,每次访问变量地址会导致大量冗余的数据cache不命中访存操作.此外,这种寻址方式会产生两条连续的有数据依赖的操作,降低了程序的指令级并行性.提出了基于反馈信息的地址寄存器提升算法(address register promotion based on feedbacks,ARPF).该算法减少了对全局变量地址和静态变量地址的冗余访问,提高了程序的ILP(instruction level parallelism),同时避免了由于寄存器压力增加导致性能下降.在龙芯编译器①上实现了该算法.实验表明ARPF对SPEC CPU2000INT所有测试用例有1%～6%的性能提升.
基金Foundation items:Fundamental Research Funds for the Central Universities(No.JUSRP51510)Primary Research&Development Plan of Jiangsu Province(No.BE2019003-2)。
文摘Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.
