以65nm双阱CMOS(Complementary Metal Oxide Semiconductor)工艺的SRAM(Static Random Access Memory)为研究对象,采用三维数值模拟方法,结合SRAM中晶体管布局和邻近SRAM的相对位置,对寄生双极晶体管效应致纳米SRAM内部节点电势多次翻...以65nm双阱CMOS(Complementary Metal Oxide Semiconductor)工艺的SRAM(Static Random Access Memory)为研究对象,采用三维数值模拟方法,结合SRAM中晶体管布局和邻近SRAM的相对位置,对寄生双极晶体管效应致纳米SRAM内部节点电势多次翻转的产生机制进行了深入阐述,对寄生双极晶体管效应致纳米SRAM发生MCU(Multiple Cell Upset)的影响因素进行了详细研究.发现寄生双极晶体管效应致SRAM内部节点电势多次翻转源于N阱中两个PMOS漏极电势的竞争过程,竞争过程与寄生双极晶体管效应的强弱相关,需综合考虑PMOS源极与N阱接触的距离、PMOS漏极与N阱的电势差两个因素.在纳米双阱CMOS工艺的SRAM中,PNP寄生双极晶体管效应对MCU起着重要作用.减小阱接触与SRAM单元的距离,可减弱邻近SRAM的寄生双极晶体管效应并降低MCU的发生概率,即使阱接触距离很近,特殊角度的斜入射和高LET(Linear Energy Transfer)值离子入射仍存在触发邻近SRAM的寄生双极晶体管效应并导致MCU的可能.展开更多
The speed of frequency response of all published carbon nanotube （CNT） integrated circuits （ICs） is far from that predicted. The transient response of CNT ICs is explored systematically through the combination of ...The speed of frequency response of all published carbon nanotube （CNT） integrated circuits （ICs） is far from that predicted. The transient response of CNT ICs is explored systematically through the combination of experimental and simulation methods. Complementary field-effect-transistor （FET） based inverters were fabricated on a single semiconducting CNT, and the dynamic response measurement indicates that it can only work at an unexpectedly low speed, i.e. with a large propagation delay of 30 }_ts. Owing to the larger output resistance of CNT FETs, the existence of parasitic capacitances should induce much larger resistive-capacitive （RC） delay than that in Si ICs. Through detailed analysis combining simulation and experimental measurements, several kinds of parasitic capacitances dragging down the actual speed of CNT FET ICs are identified one by one, and each of them limits the speed at different levels through RC delay. It is found that the parasitic capacitance from the measurement system is the dominant one, and the large RC delay lowers the speed of CNT FETs logic circuits to only several kHz which is similar to the experimental results. Various optimized schemes are suggested and demonstrated to minimize the effect of parasitic capacitances, and thus improve the speed of CNT ICs.展开更多
文摘以65nm双阱CMOS(Complementary Metal Oxide Semiconductor)工艺的SRAM(Static Random Access Memory)为研究对象,采用三维数值模拟方法,结合SRAM中晶体管布局和邻近SRAM的相对位置,对寄生双极晶体管效应致纳米SRAM内部节点电势多次翻转的产生机制进行了深入阐述,对寄生双极晶体管效应致纳米SRAM发生MCU(Multiple Cell Upset)的影响因素进行了详细研究.发现寄生双极晶体管效应致SRAM内部节点电势多次翻转源于N阱中两个PMOS漏极电势的竞争过程,竞争过程与寄生双极晶体管效应的强弱相关,需综合考虑PMOS源极与N阱接触的距离、PMOS漏极与N阱的电势差两个因素.在纳米双阱CMOS工艺的SRAM中,PNP寄生双极晶体管效应对MCU起着重要作用.减小阱接触与SRAM单元的距离,可减弱邻近SRAM的寄生双极晶体管效应并降低MCU的发生概率,即使阱接触距离很近,特殊角度的斜入射和高LET(Linear Energy Transfer)值离子入射仍存在触发邻近SRAM的寄生双极晶体管效应并导致MCU的可能.
基金This work was supported by the National Basic Research Program of China （Nos. 2011CB933001 and 2011CB933002）, the National Natural Science Foundation of China （Nos. 61322105, 61271051, 61376126, 61321001 and 61390504）, and the Beijing Municipal Science and Technology Commission （Nos. Z131100003213021 and 20121000102）.
文摘The speed of frequency response of all published carbon nanotube （CNT） integrated circuits （ICs） is far from that predicted. The transient response of CNT ICs is explored systematically through the combination of experimental and simulation methods. Complementary field-effect-transistor （FET） based inverters were fabricated on a single semiconducting CNT, and the dynamic response measurement indicates that it can only work at an unexpectedly low speed, i.e. with a large propagation delay of 30 }_ts. Owing to the larger output resistance of CNT FETs, the existence of parasitic capacitances should induce much larger resistive-capacitive （RC） delay than that in Si ICs. Through detailed analysis combining simulation and experimental measurements, several kinds of parasitic capacitances dragging down the actual speed of CNT FET ICs are identified one by one, and each of them limits the speed at different levels through RC delay. It is found that the parasitic capacitance from the measurement system is the dominant one, and the large RC delay lowers the speed of CNT FETs logic circuits to only several kHz which is similar to the experimental results. Various optimized schemes are suggested and demonstrated to minimize the effect of parasitic capacitances, and thus improve the speed of CNT ICs.
