Partial-depleted SOI(silicon on insulator) nMOS devices are fabricated with and without silicide technology,respectively.Off-state breakdown characteristics of these devices are presented with and without body contact...Partial-depleted SOI(silicon on insulator) nMOS devices are fabricated with and without silicide technology,respectively.Off-state breakdown characteristics of these devices are presented with and without body contact,respectively.By means of two-dimension(2D) device simulation and measuring junction breakdown of the drain and the body,the difference and limitation of the breakdown characteristics of devices with two technologies are analyzed and explained in details.Based on this,a method is proposed to improve off-state breakdown characteristics of PDSOI nMOS devices.展开更多
FB （floating-body） and BC （body-contact） partially depleted SOI nMOSFETs with HBC（half-back-channel） implantation are fabricated. Test results show that such devices have good performance in delaying the occurre...FB （floating-body） and BC （body-contact） partially depleted SOI nMOSFETs with HBC（half-back-channel） implantation are fabricated. Test results show that such devices have good performance in delaying the occurrence of the “kink” phenomenon and improving the breakdown voltage as compared to conventional PDSOI nMOS- FETs,while not decreasing the threshold voltage of the back gate obviously. Numerical simulation shows that a reduced electrical field in the drain contributes to the improvement of the breakdown voltage and a delay of the “kink” effect. A detailed analysis is given for the cause of such improvement of breakdown voltage and the delay of the “kink” effect.展开更多
The first domestic 1×10^6rad（Si） total dose hardened 1.2μm partially depleted silicon-on-insulator （PDSOI） 64k SRAM fabricated in SIMOX is demonstrated.The address access time is independent of temperature f...The first domestic 1×10^6rad（Si） total dose hardened 1.2μm partially depleted silicon-on-insulator （PDSOI） 64k SRAM fabricated in SIMOX is demonstrated.The address access time is independent of temperature from -55 to 125℃ and independent of radiation up to 1×10^6rad（Si） for the supply voltage VDD.The standby current is 0.65μA before the total dose of radiation and is only 0.80mA after radiation exposure,which is much better than the specified 10mA.The operating power supply current is 33.0mA before and only 38.1mA afterward,which is much better than the specified 100mA.展开更多
A new super junction LDMOST structure that suppresses the substrate-assisted depletion effect is designed with an n^＋-floating layer embedded in the high-resistance p-type substrate by implanting phosphor or arsenic....A new super junction LDMOST structure that suppresses the substrate-assisted depletion effect is designed with an n^＋-floating layer embedded in the high-resistance p-type substrate by implanting phosphor or arsenic. This effect results from a charge imbalance between the n-type and p-type pillars when the n-type pillars are depleted by p-type substrate. The high electric field around the drain is reduced by the n^＋-floating layer due to the REBULF effect,which causes the redistribution of the bulk electric field in the drift region,and thus the substrate supports more biases. The new structure features high breakdown voltage, low on-resistance,and charge balance in the drift region.展开更多
A new design concept is proposed to eliminate the substrate-assisted depletion effect that significantly degrades the breakdown voltage （BV） of conventional super junction-LDMOS. The key feature of the new concept i...A new design concept is proposed to eliminate the substrate-assisted depletion effect that significantly degrades the breakdown voltage （BV） of conventional super junction-LDMOS. The key feature of the new concept is that a partial buried layer is implemented which compensates for the charge interaction between the p-substrate and SJ region,realizing high breakdown voltage and low on-resistance. Numerical simulation results indicate that the proposed device features high breakdown voltage,low on-resistance,and reduced sensitivity to doping imbalance in the pillars. In addition, the proposed device is compatible with smart power technology.展开更多
The first domestic total dose hardened 2μm partially depleted silicon-on-insulator （PDSOI） CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transisto...The first domestic total dose hardened 2μm partially depleted silicon-on-insulator （PDSOI） CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transistor threshold voltage shifts,circuit static leakage currents,and I-V curves as a function of total dose up to 3× 10^5rad（Si）. The worst case threshold voltage shifts of the front channels are less than 20mV for nMOS transistors at 3 × 10^5rad（Si） and follow-up irradiation and less than 70mV for the pMOS transistors. Furthermore, no significant radiation induced leakage currents and functional degeneration are observed.展开更多
Modeling analysis of thin fully depleted SOICMOS technology has been done. Using ISETCAD software,the high temperature characteristics of an SOICMOS transistor were simulated in the temperature range of from 300 to 60...Modeling analysis of thin fully depleted SOICMOS technology has been done. Using ISETCAD software,the high temperature characteristics of an SOICMOS transistor were simulated in the temperature range of from 300 to 600K, and the whole circuit of a laser range finder was simulated with Verilog software. By wafer pro- cessing,a circuit of a laser range finder with complete function and parameters working at high temperatures has been developed. The simulated results agree with the test results. The test of the circuit function and parameters at normal and high temperature shows the realization of an SOICMOS integrated circuit with low power dissipation and high speed, which can be applied in laser range finding. By manufacturing this device, further study on high temperature characteristics of shorter channel SOICMOS integrated circuits can be conducted.展开更多
A Schottky gate resonant tunneling transistor （SGRTT） is fabricated. Relying on simulation by ATLAS software,we find that the gate voltages can be used to control the current of SGRTT when the emitter terminal is gr...A Schottky gate resonant tunneling transistor （SGRTT） is fabricated. Relying on simulation by ATLAS software,we find that the gate voltages can be used to control the current of SGRTT when the emitter terminal is grounded and a positive bias voltage is applied to the collector terminal. When the collector terminal is grounded, the gate voltages can control the peak voltage. As revealed by measurement results, the reason is that the gate voltages and the electric field distribution on emitter and collector terminal change the distribution of the depletion region.展开更多
A novel approximation of the two-dimensional （2D） potential function perpendicular to the channel is proposed,and then an analytical threshold voltage model for a fully depleted SOI-MOSFET with a non-uniform Gaussia...A novel approximation of the two-dimensional （2D） potential function perpendicular to the channel is proposed,and then an analytical threshold voltage model for a fully depleted SOI-MOSFET with a non-uniform Gaussian distribution doping profile is given based on this approximation. The model agrees well with numerical simulation by MEDICI. The result represents a new way and some reference points in analyzing and controlling the threshold voltage of non-uniform fully depleted （FD） SOI devices in practice.展开更多
文摘Partial-depleted SOI(silicon on insulator) nMOS devices are fabricated with and without silicide technology,respectively.Off-state breakdown characteristics of these devices are presented with and without body contact,respectively.By means of two-dimension(2D) device simulation and measuring junction breakdown of the drain and the body,the difference and limitation of the breakdown characteristics of devices with two technologies are analyzed and explained in details.Based on this,a method is proposed to improve off-state breakdown characteristics of PDSOI nMOS devices.
文摘FB （floating-body） and BC （body-contact） partially depleted SOI nMOSFETs with HBC（half-back-channel） implantation are fabricated. Test results show that such devices have good performance in delaying the occurrence of the “kink” phenomenon and improving the breakdown voltage as compared to conventional PDSOI nMOS- FETs,while not decreasing the threshold voltage of the back gate obviously. Numerical simulation shows that a reduced electrical field in the drain contributes to the improvement of the breakdown voltage and a delay of the “kink” effect. A detailed analysis is given for the cause of such improvement of breakdown voltage and the delay of the “kink” effect.
文摘The first domestic 1×10^6rad（Si） total dose hardened 1.2μm partially depleted silicon-on-insulator （PDSOI） 64k SRAM fabricated in SIMOX is demonstrated.The address access time is independent of temperature from -55 to 125℃ and independent of radiation up to 1×10^6rad（Si） for the supply voltage VDD.The standby current is 0.65μA before the total dose of radiation and is only 0.80mA after radiation exposure,which is much better than the specified 10mA.The operating power supply current is 33.0mA before and only 38.1mA afterward,which is much better than the specified 100mA.
文摘A new super junction LDMOST structure that suppresses the substrate-assisted depletion effect is designed with an n^＋-floating layer embedded in the high-resistance p-type substrate by implanting phosphor or arsenic. This effect results from a charge imbalance between the n-type and p-type pillars when the n-type pillars are depleted by p-type substrate. The high electric field around the drain is reduced by the n^＋-floating layer due to the REBULF effect,which causes the redistribution of the bulk electric field in the drift region,and thus the substrate supports more biases. The new structure features high breakdown voltage, low on-resistance,and charge balance in the drift region.
文摘A new design concept is proposed to eliminate the substrate-assisted depletion effect that significantly degrades the breakdown voltage （BV） of conventional super junction-LDMOS. The key feature of the new concept is that a partial buried layer is implemented which compensates for the charge interaction between the p-substrate and SJ region,realizing high breakdown voltage and low on-resistance. Numerical simulation results indicate that the proposed device features high breakdown voltage,low on-resistance,and reduced sensitivity to doping imbalance in the pillars. In addition, the proposed device is compatible with smart power technology.
文摘The first domestic total dose hardened 2μm partially depleted silicon-on-insulator （PDSOI） CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transistor threshold voltage shifts,circuit static leakage currents,and I-V curves as a function of total dose up to 3× 10^5rad（Si）. The worst case threshold voltage shifts of the front channels are less than 20mV for nMOS transistors at 3 × 10^5rad（Si） and follow-up irradiation and less than 70mV for the pMOS transistors. Furthermore, no significant radiation induced leakage currents and functional degeneration are observed.
文摘Modeling analysis of thin fully depleted SOICMOS technology has been done. Using ISETCAD software,the high temperature characteristics of an SOICMOS transistor were simulated in the temperature range of from 300 to 600K, and the whole circuit of a laser range finder was simulated with Verilog software. By wafer pro- cessing,a circuit of a laser range finder with complete function and parameters working at high temperatures has been developed. The simulated results agree with the test results. The test of the circuit function and parameters at normal and high temperature shows the realization of an SOICMOS integrated circuit with low power dissipation and high speed, which can be applied in laser range finding. By manufacturing this device, further study on high temperature characteristics of shorter channel SOICMOS integrated circuits can be conducted.
文摘A Schottky gate resonant tunneling transistor （SGRTT） is fabricated. Relying on simulation by ATLAS software,we find that the gate voltages can be used to control the current of SGRTT when the emitter terminal is grounded and a positive bias voltage is applied to the collector terminal. When the collector terminal is grounded, the gate voltages can control the peak voltage. As revealed by measurement results, the reason is that the gate voltages and the electric field distribution on emitter and collector terminal change the distribution of the depletion region.
文摘A novel approximation of the two-dimensional （2D） potential function perpendicular to the channel is proposed,and then an analytical threshold voltage model for a fully depleted SOI-MOSFET with a non-uniform Gaussian distribution doping profile is given based on this approximation. The model agrees well with numerical simulation by MEDICI. The result represents a new way and some reference points in analyzing and controlling the threshold voltage of non-uniform fully depleted （FD） SOI devices in practice.
