This paper presents the design and implementation of a low power digital signal processor （THUCIDSP-1 ） targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimizati...This paper presents the design and implementation of a low power digital signal processor （THUCIDSP-1 ） targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimization, operand isolation, clock gating and memory partitioning are adopted in the processor design to reduce the power consumption. Experimental results show that the complexity of the Continuous Interleaved Sampling （CIS） algorithm is reduced by more than 80 % and the power dissipation of the hardware alone is reduced by about 25% with the low power methods. The THUCIDSP-1 prototype, fabricated in 0.18-μm standard CMOS process, consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.展开更多
This paper is concerned with the fractional version of online hierarchical scheduling problem on uniform machines.In the problem,the jobs and machines have several different hierarchies and each job can be arbitrarily...This paper is concerned with the fractional version of online hierarchical scheduling problem on uniform machines.In the problem,the jobs and machines have several different hierarchies and each job can be arbitrarily split between the machines with hierarchies not above the hierarchy of the job.The objective is to minimize the makespan.The authors present an optimal algorithm for the problem with three hierarchies.展开更多
基金Supported by the National Natural Science Foundation of China (No. 60475018)
文摘This paper presents the design and implementation of a low power digital signal processor （THUCIDSP-1 ） targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimization, operand isolation, clock gating and memory partitioning are adopted in the processor design to reduce the power consumption. Experimental results show that the complexity of the Continuous Interleaved Sampling （CIS） algorithm is reduced by more than 80 % and the power dissipation of the hardware alone is reduced by about 25% with the low power methods. The THUCIDSP-1 prototype, fabricated in 0.18-μm standard CMOS process, consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.
基金supported by National Natural Science Foundation of China under Grant No.11171106
文摘This paper is concerned with the fractional version of online hierarchical scheduling problem on uniform machines.In the problem,the jobs and machines have several different hierarchies and each job can be arbitrarily split between the machines with hierarchies not above the hierarchy of the job.The objective is to minimize the makespan.The authors present an optimal algorithm for the problem with three hierarchies.
