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中枢神经信号微电子技术检测、处理与重建研究 被引量:3
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作者 王志功 吕晓迎 顾晓松 《通讯和计算机(中英文版)》 2004年第1期77-81,52,共6页
介绍国内外利用微电子技术实现中枢神经信号检测、处理与再生的研究状况与进展。研究神经电信号检测的电极装置、中枢神经电信号处理和功能控制的专用集成电路、远端神经信号再生的刺激装置、生物体植入式芯片的供电方式、低功耗电路的... 介绍国内外利用微电子技术实现中枢神经信号检测、处理与再生的研究状况与进展。研究神经电信号检测的电极装置、中枢神经电信号处理和功能控制的专用集成电路、远端神经信号再生的刺激装置、生物体植入式芯片的供电方式、低功耗电路的设计技术一系列技术,电极装置、生物体植入式芯片和刺激装置的生物相容性和显微植入手术等一系列课题。 展开更多
关键词 中枢神经功能重建 生物体嵌入式集成电路 生物材料生物相容性 植入手术
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Cirrus Logic完成其数字视频产品线的出售
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《中国集成电路》 2005年第8期7-7,共1页
Cirrus Logic公司最近宣布已经完成将其数字视频产品线出售给Magnum半导体公司的交易。售出其数字视频产品线后,Cirrus Logic公司将专注于面向音频和工业市场的核心模拟。混合信号以及嵌入式集成电路(IC)产品的研发。此次交易采取资... Cirrus Logic公司最近宣布已经完成将其数字视频产品线出售给Magnum半导体公司的交易。售出其数字视频产品线后,Cirrus Logic公司将专注于面向音频和工业市场的核心模拟。混合信号以及嵌入式集成电路(IC)产品的研发。此次交易采取资产转让形式。Cirrus Logic公司将持有Magnum半导体公司的少量股份。并以成本记账形式支付。 展开更多
关键词 数字视频产品线 嵌入式集成电路 专用集成电路 CIRRUS Logic公司
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A HIGH-PERFORMANCE VLSI ARCHITECTURE OF EBCOT BLOCK CODING IN JPEG2000 被引量:1
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作者 Liu Kai Wu Chengke Li Yunsong 《Journal of Electronics(China)》 2006年第1期89-93,共5页
The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of e... The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of each bit plane can be obtained simultaneously and processed parallel. Compared with other architectures, it has advantages of high parallelism, and no waste clock cycles for a single point. The experimental results show that it reduces the processing time about 86% than that of bit plane sequential scheme. A Field Programmable Gate Array (FPGA) prototype chip is designed and simulation results show that it can process 512×512 gray-scaled images with more than 30 frames per second at 52MHz. 展开更多
关键词 JPEG2000 Embedded Block Coding with Optimized Truncation (EBCOT) Bit plane-parallel Block encoder Context model
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Multilevel Power Modeling of Base Station and Its ICs 被引量:1
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作者 WANG Wei LI Xiaoyang +2 位作者 LIU Dake CAI Zhaoyun GONG Chen 《China Communications》 SCIE CSCD 2015年第5期22-33,共12页
A new power estimation method is proposed for base station(BS) in this paper.Based on this method,a software platform for power estimation is developed.The proposed method models power consumption on different abstrac... A new power estimation method is proposed for base station(BS) in this paper.Based on this method,a software platform for power estimation is developed.The proposed method models power consumption on different abstraction levels by splitting a typical base station into several basic components at different levels in the view of embedded system design.In particular,our focus is on baseband IC(Integrate Circuit) due to it's the dominant power consumer in small cells.Baseband power model is based on arithmetic computing costs of selected algorithms.All computing and storage costs are calibrated using algorithm complexity,hardware architecture,activity ratio,silicon technology,and overheads on all hierarchies.Micro architecture and IC technology are considered.The model enables power comparison of different types of base stations configured with different baseband algorithms,micro architectures,and ICs.The model also supports cellular operators in power estimation of different deployment strategies and transmission schemes.The model is verified by comparing power consumption with a real LTE base station.By exposing more configuration freedoms,the platform can be used for power estimation of current and future base stations. 展开更多
关键词 baseband IC power consumption power modeling base station 5G
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