A down-conversion mixer and an up-conversion mixer for 2.4GHz WLAN transceivers are presented.The down-conversion mixer uses a class-AB input stage to get high linearity and to realize input impedance matching and sin...A down-conversion mixer and an up-conversion mixer for 2.4GHz WLAN transceivers are presented.The down-conversion mixer uses a class-AB input stage to get high linearity and to realize input impedance matching and single-ended to differential conversion.The mixers are implemented in 0.18μm CMOS process.The measured results are given to show their performance.展开更多
A 12 Gbit/s limiting amplifier for fiber-optic transmission system is realized in a 2μm GaAs HBT technology. The whole circuit consists of an input buffer, three similar amplifier cells, an output buffer for driving ...A 12 Gbit/s limiting amplifier for fiber-optic transmission system is realized in a 2μm GaAs HBT technology. The whole circuit consists of an input buffer, three similar amplifier cells, an output buffer for driving 50 ft transmission lines and a pair of feedback networks for offset cancellation. At a positive supply voltage of 2 V and a negative supply voltage of - 2V, the power dissipation is about 280 mW. The small-signal gain is higher than 46 dB and the input dynamic range is about 40 dB with a constant single-ended output voltage swing of 400 mV. Satisfactory eye-diagrams are obtained at the bit rate of 12 Gbit/s limited by the test set-up. The chip area is 1.15 mm ×0.7 mm.展开更多
文摘A down-conversion mixer and an up-conversion mixer for 2.4GHz WLAN transceivers are presented.The down-conversion mixer uses a class-AB input stage to get high linearity and to realize input impedance matching and single-ended to differential conversion.The mixers are implemented in 0.18μm CMOS process.The measured results are given to show their performance.
文摘A 12 Gbit/s limiting amplifier for fiber-optic transmission system is realized in a 2μm GaAs HBT technology. The whole circuit consists of an input buffer, three similar amplifier cells, an output buffer for driving 50 ft transmission lines and a pair of feedback networks for offset cancellation. At a positive supply voltage of 2 V and a negative supply voltage of - 2V, the power dissipation is about 280 mW. The small-signal gain is higher than 46 dB and the input dynamic range is about 40 dB with a constant single-ended output voltage swing of 400 mV. Satisfactory eye-diagrams are obtained at the bit rate of 12 Gbit/s limited by the test set-up. The chip area is 1.15 mm ×0.7 mm.
