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多核微处理器体系结构级功耗模型分析 被引量:2
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作者 陈卓 刘畅 +1 位作者 侯申 郭阳 《中南大学学报(自然科学版)》 EI CAS CSCD 北大核心 2019年第7期1611-1618,共8页
利用FT-SHSim 模拟工具平台,对主流的微处理器核心模型SMT(同步多线程,simultaneous multithreading)和MSS(适度超标量,moderate superscalar)进行建模。采用先进CMOS工艺,在体系结构级进行功耗评估的模拟实验,得到不同微处理器结构的... 利用FT-SHSim 模拟工具平台,对主流的微处理器核心模型SMT(同步多线程,simultaneous multithreading)和MSS(适度超标量,moderate superscalar)进行建模。采用先进CMOS工艺,在体系结构级进行功耗评估的模拟实验,得到不同微处理器结构的工艺需求和不同工艺下同微处理器结构可以实现的性能及所需的规模,为微处理器设计的早期阶段提供工艺需求与实现方法的参考价值,从而实现提高设计质量、缩短设计周期、加快设计收敛的目的。研究结果表明:在最小线宽为22nm的工艺下,128 核SMT处理器模型峰值功耗为116W,64核MSS处理器峰值功耗为161W。 展开更多
关键词 多核处理器 体系结构级 峰值功耗 工艺模拟器
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Design of a(480,240)CMOS Analog Low-Density Parity-Check Decoder
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作者 Hao Zheng Zhe Zhao +1 位作者 Xiangming Li Hangcheng Han 《China Communications》 SCIE CSCD 2017年第8期41-53,共13页
Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is cons... Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue to some extent. However, due to the lack of automation tools and analog stopping criteria, the analog LDPC decoders suffer from costly handcraft design and additional decoding delay, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and implemented to reduce the decoding delay. Then, a(480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35-μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3m W, and the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works. 展开更多
关键词 LDPC analog decoder handcraft design reduction probability stopping criterion for analog decoding reusable building block
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Development of an Emulator for the Plasma Process Control
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作者 Marie-Pierre Planche Taikai Liu Sihao Deng Ghislain Montavon 《Journal of Mechanics Engineering and Automation》 2015年第1期10-18,共9页
This work aims at developing an automatic system for the control of the APS (air plasma spraying) plasma process in which some instability phenomena are present. APS is a versatile technique to produce coatings of p... This work aims at developing an automatic system for the control of the APS (air plasma spraying) plasma process in which some instability phenomena are present. APS is a versatile technique to produce coatings of powder material at high deposition rates. Using this technique, powder particles are injected into a plasma jet, where they are melted and accelerated towards a substrate. The coating microstructures and properties depend strongly on the characteristics of the plasma jet, which can be controlled by the adjustment of the process parameters. However, the imeractions among the spray variables, render optimization and control of this process are quite complex. Understanding relationships between coating properties and process parameters is mandatory to optimize the process technique and the product quality. We are interested in this work to build an on-line control model for the APS process based on the elements of artificial intelligence and to build an emulator that replicates the dynamic behavior of the process as closely as possible. 展开更多
关键词 Atmospheric plasma spray process parameters artificial neural networks fuzzy logic EMULATOR
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