Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementat...Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.展开更多
In the knowledge economy era,science and technology(S&T) resources are getting more and more important in shaping regional competiveness and building regional innovation capacity.As such,the spatial distribution o...In the knowledge economy era,science and technology(S&T) resources are getting more and more important in shaping regional competiveness and building regional innovation capacity.As such,the spatial distribution of S&T resources is a key to understanding regional development and disparities.By designing an input-output indicator system,this paper develops an evaluation model to examine the spatial distribution of S&T resources in China and assess their spatial efficiency.Moreover,the paper tries to explain spatial differences in the efficiency of S&T resources in China.Major findings are:1) the input and output of S&T resources in China shows a clear T-shaped spatial structure,i.e.,concentrated mainly in the coastal region and along the Changjiang(Yangtze) River;2) the efficiency of S&T resources in China displays strong spatial disparities,with the level of efficiency descending from the east to the west while high efficiency appearing in only several clusters;3) the utilization rates of S&T resources in most provinces are quite low,resulting in low efficiency of S&T resources allocation.The paper suggests that the utilization rate of S&T resources should be raised and the commercialization of S&T outputs should be enhanced to improve the efficiency of S&T resources in China.展开更多
文摘Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.
基金Under the auspices of National Science Fund for Distinguished Young Scholars(No.41125005)
文摘In the knowledge economy era,science and technology(S&T) resources are getting more and more important in shaping regional competiveness and building regional innovation capacity.As such,the spatial distribution of S&T resources is a key to understanding regional development and disparities.By designing an input-output indicator system,this paper develops an evaluation model to examine the spatial distribution of S&T resources in China and assess their spatial efficiency.Moreover,the paper tries to explain spatial differences in the efficiency of S&T resources in China.Major findings are:1) the input and output of S&T resources in China shows a clear T-shaped spatial structure,i.e.,concentrated mainly in the coastal region and along the Changjiang(Yangtze) River;2) the efficiency of S&T resources in China displays strong spatial disparities,with the level of efficiency descending from the east to the west while high efficiency appearing in only several clusters;3) the utilization rates of S&T resources in most provinces are quite low,resulting in low efficiency of S&T resources allocation.The paper suggests that the utilization rate of S&T resources should be raised and the commercialization of S&T outputs should be enhanced to improve the efficiency of S&T resources in China.
