We present a deterministic algorithm for large-scale VLSI module placement. Following the less flexibility first （LFF） principle,we simulate a manual packing process in which the concept of placement by stages is in...We present a deterministic algorithm for large-scale VLSI module placement. Following the less flexibility first （LFF） principle,we simulate a manual packing process in which the concept of placement by stages is introduced to reduce the overall evaluation complexity. The complexity of the proposed algorithm is （N1 ＋ N2 ） × O（ n^2 ） ＋ N3× O（n^4lgn） ,where N1, N2 ,and N3 denote the number of modules in each stage, N1 ＋ N2 ＋ N3 = n, and N3〈〈 n. This complexity is much less than the original time complexity of O（n^5lgn）. Experimental results indicate that this approach is quite promising.展开更多
The automatic schematic diagram generator of BIT (ASG-BIT) discussed here is a subsystem of the VHDL high-level synthesis and mixed-level simulation system (HLS-BIT). It can abstract netlists from the result of logic ...The automatic schematic diagram generator of BIT (ASG-BIT) discussed here is a subsystem of the VHDL high-level synthesis and mixed-level simulation system (HLS-BIT). It can abstract netlists from the result of logic synthesis and generates functionally readable and aesthetically pleasing diagrams within reasonable execution time. The partitioning, placement and routing of schematic diagram are discussed .and some results including several diagrams generated by ASG-BIT system are presented in the finale of this paper.展开更多
文摘We present a deterministic algorithm for large-scale VLSI module placement. Following the less flexibility first （LFF） principle,we simulate a manual packing process in which the concept of placement by stages is introduced to reduce the overall evaluation complexity. The complexity of the proposed algorithm is （N1 ＋ N2 ） × O（ n^2 ） ＋ N3× O（n^4lgn） ,where N1, N2 ,and N3 denote the number of modules in each stage, N1 ＋ N2 ＋ N3 = n, and N3〈〈 n. This complexity is much less than the original time complexity of O（n^5lgn）. Experimental results indicate that this approach is quite promising.
文摘The automatic schematic diagram generator of BIT (ASG-BIT) discussed here is a subsystem of the VHDL high-level synthesis and mixed-level simulation system (HLS-BIT). It can abstract netlists from the result of logic synthesis and generates functionally readable and aesthetically pleasing diagrams within reasonable execution time. The partitioning, placement and routing of schematic diagram are discussed .and some results including several diagrams generated by ASG-BIT system are presented in the finale of this paper.
