An efficient partitioning algorithm for mixed-mode placement,extended-MFFC-based partitioning,is presented.It combines the bottom-up clustering and the top-down partitioning together.To do this,designers can not only ...An efficient partitioning algorithm for mixed-mode placement,extended-MFFC-based partitioning,is presented.It combines the bottom-up clustering and the top-down partitioning together.To do this,designers can not only cluster cells considering logic dependency but also partition them aiming at min-cut.Experimental results show that extended-MFFC-based partitioning performs well in mixed-mode placement with big pre-designed blocks.By comparison with the famous partitioning package HMETIS,this partitioning proves its remarkable function in mixed-mode placement.展开更多
A method of combining the MFFC clustering and hMETIS partitioning based quadratic placement algorithm is proposed. Experimental results show that it can gain good results but consume long running time.In order to cut...A method of combining the MFFC clustering and hMETIS partitioning based quadratic placement algorithm is proposed. Experimental results show that it can gain good results but consume long running time.In order to cut down the running time,an improved MFFC clustering method (IMFFC) based Q-place algorithm is proposed.Comparing with the combining clustering and partitioning based method,it is much faster but with a little increase in total wire length.展开更多
The automatic schematic diagram generator of BIT (ASG-BIT) discussed here is a subsystem of the VHDL high-level synthesis and mixed-level simulation system (HLS-BIT). It can abstract netlists from the result of logic ...The automatic schematic diagram generator of BIT (ASG-BIT) discussed here is a subsystem of the VHDL high-level synthesis and mixed-level simulation system (HLS-BIT). It can abstract netlists from the result of logic synthesis and generates functionally readable and aesthetically pleasing diagrams within reasonable execution time. The partitioning, placement and routing of schematic diagram are discussed .and some results including several diagrams generated by ASG-BIT system are presented in the finale of this paper.展开更多
文摘An efficient partitioning algorithm for mixed-mode placement,extended-MFFC-based partitioning,is presented.It combines the bottom-up clustering and the top-down partitioning together.To do this,designers can not only cluster cells considering logic dependency but also partition them aiming at min-cut.Experimental results show that extended-MFFC-based partitioning performs well in mixed-mode placement with big pre-designed blocks.By comparison with the famous partitioning package HMETIS,this partitioning proves its remarkable function in mixed-mode placement.
文摘A method of combining the MFFC clustering and hMETIS partitioning based quadratic placement algorithm is proposed. Experimental results show that it can gain good results but consume long running time.In order to cut down the running time,an improved MFFC clustering method (IMFFC) based Q-place algorithm is proposed.Comparing with the combining clustering and partitioning based method,it is much faster but with a little increase in total wire length.
文摘The automatic schematic diagram generator of BIT (ASG-BIT) discussed here is a subsystem of the VHDL high-level synthesis and mixed-level simulation system (HLS-BIT). It can abstract netlists from the result of logic synthesis and generates functionally readable and aesthetically pleasing diagrams within reasonable execution time. The partitioning, placement and routing of schematic diagram are discussed .and some results including several diagrams generated by ASG-BIT system are presented in the finale of this paper.
