An efficient design method for a 24 × 24 bit ＋48 bit parallel saturating multiply-accumulate （MAC） unit is described. The augend in the MAC is merged as a partial product into Wallace tree array. The optimized...An efficient design method for a 24 × 24 bit ＋48 bit parallel saturating multiply-accumulate （MAC） unit is described. The augend in the MAC is merged as a partial product into Wallace tree array. The optimized saturation detection logic is proposed. The 679. 2 μm × 132. 5μm area size has been achieved in 0. 18 μm 1.8 V 1P6M CMOS technology by the full-custom circuit layout design. The simulation results show that the design way has significantly less area （about 23.52% reduction） and less delay than those of the common saturating MAC based on standard cell library.展开更多
基金The National Natural Science Foundation of China(No.90407009),the National High Technology Research and Develop-ment Program of China(863Program) (No.2003AA1Z1340)
文摘An efficient design method for a 24 × 24 bit ＋48 bit parallel saturating multiply-accumulate （MAC） unit is described. The augend in the MAC is merged as a partial product into Wallace tree array. The optimized saturation detection logic is proposed. The 679. 2 μm × 132. 5μm area size has been achieved in 0. 18 μm 1.8 V 1P6M CMOS technology by the full-custom circuit layout design. The simulation results show that the design way has significantly less area （about 23.52% reduction） and less delay than those of the common saturating MAC based on standard cell library.
