清華簡《厚父》篇所謂“乎”字考——兼論平、乎、兮一系字的釋讀

清華簡《厚父》篇整理本有“少命咎陶下爲之卿事”一句,其中“少”字,簡文作■。諸家多有説解而皆有疑問。問題的根源在於現有文字學研究對“平”“乎”及“兮”一系字多有誤解。這一誤解最早源於羅振玉,今人延續之而不察。通過字形排比,我們廓清此數字的源流。清華簡此字應隸爲“平”。《爾雅·釋詁》:“俾、拼、抨,使也。”郭注:“皆謂使令。”“平命咎陶下爲之卿事”,意即“使令皋陶下爲之卿事”。此句反映了上古三代充滿神性意味的君臣關係。

Formal Analysis of Trusted Platform Module Commands for Compromising User Key

The Trusted Platform Module （TPM） is a dedicated hardware chip designed to provide a higher level of security for computing platform. All TPM functionalities are implemented in TPM corntrends to achieve specific security goals. We attempt to analyze the security properties of these commands, especially the key management API. Our study utilizes applied pi calculus to forrmlize the commands and determine how their security properties affect TPM key rmnagement. The attacker is assumed to call TPM comrmnds without bounds and without knowing the TPM root key, expecting to obtain or replace the user key. The analysis goal in our study is to guarantee the corre- sponding property of API execution and the integrity of API data. We analyze the security properties of TPM commands with a process reduction method, identify the key-handle hijack attack on a TPM newly created key, and propose reasonable solutions to solve the problem. Then, we conduct an experiment involving a key-handle attack, which suc- cessfully replaces a user key with an attacker＇s key using lmlicious TPM software. This paper discloses the weakness of the relationship between the key handle and the key object. After the TPM software stack is compromised, the attacker can hunch a keyhandle attack to obtain the user key and even break into the whole storage tree of user keys.

A parallel memory architecture for video coding

To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements （8-bit and 16-bit data types） or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-pm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor （VSP）. The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.

Parameter identification of inertially stabilized platforms using current command design

Accurate parameter identification is essential when designing controllers for inertially stabilized platforms （lSPs）. But traditional identification methods suffer from observation measurement noise and operating restrictions of ISPs. To address this issue, a novel identification method based on current command design and multilevel coordinate search （MCS） algorithm without any higher order measurement differentiations was proposed. The designed current commands were adopted to obtain parameter decoupled models with the platform operating under allowable conditions. MCS algorithm was employed to estimate the parameters based on parameter decoupled models. A comparison experiment between the proposed method and non-linear least square method was carried out and most of the relative errors of identified parameters obtained by the proposed method were below 10%. Simulation and experiment based on identified parameters were conducted. A velocity control structure was also developed with disturbance observer （DOB） for application in disturbance compensation control system of an ISR Experimental results show that the control scheme based on the identified parameters with DOB has the best disturbance rejection performance. It reduces the peak to peak value （PPV） of velocity error integral to 0.8 mrad which is much smaller than the value （10 mrad） obtained by the single velocity controller without DOB. Compared with the control scheme based on sweep model with DOB compensation, the proposed control scheme improves the PPV of velocity error integral by 1.625 times.

Wavelength Converter Information Sharing in GMPLS Controlled Optical Networks

Wavelength converters are used in optical networks to overcome transparent wavelength channel insufficiency. However, current GMPLS control plane does not distribute wavelength con- verter information to network nodes. To overcome this situation, four wavelength converter information sharing methods for GMPLS-controUed optical networks are proposed. The first two, Conversion Capability during Signaling （CCS） and Conversion Availability during Signaling （CAS）, are based on the RSVP-TE signaling protocol, while the others, Conversion Capability Advertisement （CCA） and Conversion Availability Advertisement （ CAA ） , are based on the OSPF-TE routing protocol. Simulations show that CAA obtains the lowest blocking, while CCS the highest. Moreover, CAA only slightly increases the control plane load compared to CAS.

Using Pipeline Instructions by Parallel Simulation of Mathematical Models

Simulation is an important and useful technique helping users understand and model real life systems. Once built, the models can run proving realistic results. This supports making decisions on a more logical and scientific basis. The paper introduces method of simulation, and describes various types of its application. The authors used the method of analysis of the creation and implementation of the programme code. The authors compared parallel instruction of computing defined to pipelined instructions. The power of simulation is that a common model can be used to design a large variety of systems. An important aspect of the simulation method is that a simulation model is designed to be repeated in actual computer systems, especially in multicore processors. For this reason, it is important to minimize average waiting time for fetch and decode stage instructions. The objective of the research is to prove that the parallel operation of programme code is faster than sequential operation code on the multi processor architecture. The system modeling uses methods and simulation on the parallel computer systems is very precise. The time benefit gained in simulation of mathematical model on the pipeline processor is higher than the one in simulation of mathematical model on the multi processors computer system.