为解决电气化铁路牵引供电系统中三相网侧谐波、无功和负序等电能质量问题,同时满足电气化铁路补偿容量大的要求,提出了采用并联型铁路功率调节器(railway static power conditioner,RPC)配合降压变压器的综合补偿方案,具体研究了并联型...为解决电气化铁路牵引供电系统中三相网侧谐波、无功和负序等电能质量问题,同时满足电气化铁路补偿容量大的要求,提出了采用并联型铁路功率调节器(railway static power conditioner,RPC)配合降压变压器的综合补偿方案,具体研究了并联型RPC的控制策略并进行了仿真分析。提出了对RPC的指令电流检测采用平衡补偿电流检测法,对RPC的补偿电流控制采用基于比例谐振(proportion resonance,PR)控制器的三角波比较控制方式,同时将载波相移(carrier phase shift,CPS)技术应用于RPC的控制。最后,利用MATLAB/Simulink搭建了由2个RPC并联构成的补偿方案的仿真模型。仿真结果表明:RPC投入运行后,三相网侧电流为与电网电压同相位的三相正弦对称电流,只含有开关频率整数倍次的高次谐波;通过进一步采用CPS技术,开关频率奇数倍次的高次谐波被有效滤除,三相网侧电流总谐波畸变率由8.04%降低为2.24%。仿真结果验证了并联型RPC在解决牵引供电系统中三相网侧电流谐波、无功和负序等电能质量问题方面的可行性与优越性,为并联型RPC的工程应用提供了有价值的参考。展开更多
A high-speed and high-res ol ution optical A/D quantizer is proposed. Its architecture is discussed. Bit circ uits are built by using the phase modulators in parallel. Based on the different character of the half-wave...A high-speed and high-res ol ution optical A/D quantizer is proposed. Its architecture is discussed. Bit circ uits are built by using the phase modulators in parallel. Based on the different character of the half-wave voltage for every phase modulator and the polari zed bias design of incident light, the RF input signal is coded and transmitted in the form of optical digital signal. According to the principle of the archit ecture, the high-resolution quantizers with 8-bit and 12-bit, et al. are bui lt, which operate at 100 GS/ s. Their quantization noise is invariable almost w ith bit circuits increasing. The simulation result of 4-bit A/D quantizer is al so given.展开更多
基金Natural Science Foundation from Colleges and Universities of Jiangsu Province(04KJD140033)
文摘A high-speed and high-res ol ution optical A/D quantizer is proposed. Its architecture is discussed. Bit circ uits are built by using the phase modulators in parallel. Based on the different character of the half-wave voltage for every phase modulator and the polari zed bias design of incident light, the RF input signal is coded and transmitted in the form of optical digital signal. According to the principle of the archit ecture, the high-resolution quantizers with 8-bit and 12-bit, et al. are bui lt, which operate at 100 GS/ s. Their quantization noise is invariable almost w ith bit circuits increasing. The simulation result of 4-bit A/D quantizer is al so given.
